diff options
| author | Bipin Ravi <bipin.ravi@arm.com> | 2022-01-18 01:59:06 -0600 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2022-03-10 23:57:14 -0600 |
| commit | 1fe4a9d181ead0dcb2bc494e90552d3e7f0aaf4c (patch) | |
| tree | a07f088625a7eea44aa57604ed6202e9f814b3b0 /lib/cpus/aarch64/neoverse_n1.S | |
| parent | fee7b2d3b4dc4fcf225c5191a7aad8427489ef64 (diff) | |
fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
Diffstat (limited to 'lib/cpus/aarch64/neoverse_n1.S')
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 9c97cf60a..b75b0c17f 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,8 +8,8 @@ #include <asm_macros.S> #include <cpuamu.h> #include <cpu_macros.S> -#include <context.h> #include <neoverse_n1.h> +#include "wa_cve_2022_23960_bhb_vector.S" /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 @@ -23,6 +23,10 @@ .global neoverse_n1_errata_ic_trap_handler +#if WORKAROUND_CVE_2022_23960 + wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1 +#endif /* WORKAROUND_CVE_2022_23960 */ + /* -------------------------------------------------- * Errata Workaround for Neoverse N1 Erratum 1043202. * This applies to revision r0p0 and r1p0 of Neoverse N1. @@ -464,6 +468,15 @@ func check_errata_1946160 b cpu_rev_var_range endfunc check_errata_1946160 +func check_errata_cve_2022_23960 +#if WORKAROUND_CVE_2022_23960 + mov x0, #ERRATA_APPLIES +#else + mov x0, #ERRATA_MISSING +#endif + ret +endfunc check_errata_cve_2022_23960 + func neoverse_n1_reset_func mov x19, x30 @@ -575,6 +588,15 @@ func neoverse_n1_reset_func bl errata_dsu_936184_wa #endif +#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 + /* + * The Neoverse-N1 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + adr x0, wa_cve_vbar_neoverse_n1 + msr vbar_el3, x0 +#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ + isb ret x19 endfunc neoverse_n1_reset_func @@ -624,6 +646,7 @@ func neoverse_n1_errata_report report_errata ERRATA_N1_1868343, neoverse_n1, 1868343 report_errata ERRATA_N1_1946160, neoverse_n1, 1946160 report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 + report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960 ldp x8, x30, [sp], #16 ret |