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authorBoyan Karatotev <boyan.karatotev@arm.com>2022-10-03 14:18:28 +0100
committerBoyan Karatotev <boyan.karatotev@arm.com>2022-10-27 13:46:52 +0100
commit79544126943a90d31d81177655be11f75330ffed (patch)
treef4d49f21d5b4ccdf93726bba498f26de0ce0157f /lib/cpus/aarch64/cortex_x3.S
parent43438ad1ad6651964e9ae75d35f40aed8d86d088 (diff)
fix(cpus): workaround for Cortex-X3 erratum 2313909
Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions r0p0 and r1p0, and is fixed in r1p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset. SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I5935b4bcd1e6712477c0d6eab2acc96d7964a35d
Diffstat (limited to 'lib/cpus/aarch64/cortex_x3.S')
-rw-r--r--lib/cpus/aarch64/cortex_x3.S36
1 files changed, 36 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 874d565c8..bf1b6ec4a 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -31,6 +31,13 @@
* ----------------------------------------------------
*/
func cortex_x3_core_pwr_dwn
+#if ERRATA_X3_2313909
+ mov x15, x30
+ bl cpu_get_rev_var
+ bl errata_cortex_x3_2313909_wa
+ mov x30, x15
+#endif /* ERRATA_X3_2313909 */
+
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
@@ -68,6 +75,34 @@ func cortex_x3_reset_func
ret
endfunc cortex_x3_reset_func
+/* ----------------------------------------------------------------------
+ * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
+ * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * ----------------------------------------------------------------------
+ */
+func errata_cortex_x3_2313909_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2313909
+ cbz x0, 1f
+
+ /* Set bit 36 in ACTLR2_EL1 */
+ mrs x1, CORTEX_X3_CPUACTLR2_EL1
+ orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
+ msr CORTEX_X3_CPUACTLR2_EL1, x1
+1:
+ ret x17
+endfunc errata_cortex_x3_2313909_wa
+
+func check_errata_2313909
+ /* Applies to r0p0 and r1p0 */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_2313909
+
#if REPORT_ERRATA
/*
* Errata printing function for Cortex-X3. Must follow AAPCS.
@@ -82,6 +117,7 @@ func cortex_x3_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
+ report_errata ERRATA_X3_2313909, cortex_x3, 2313909
report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
ldp x8, x30, [sp], #16