diff options
| author | Sona Mathew <sonarebecca.mathew@arm.com> | 2023-09-05 14:10:03 -0500 |
|---|---|---|
| committer | Sona Mathew <sonarebecca.mathew@arm.com> | 2023-09-07 16:31:47 -0500 |
| commit | 5b0e4438d0e604e80ffff17d02e37cae0f4b2a8f (patch) | |
| tree | 152b56c8a8faf1f2a89d41bd92fa69785212e1d3 /lib/cpus/aarch64/cortex_x3.S | |
| parent | 9c16521606b1269ef13a69ec450b8d14ef92bde9 (diff) | |
fix(cpus): workaround for Cortex-X3 erratum 2742421
Cortex-X3 erratum 2742421 is a Cat B erratum that applies to
all revisions <= r1p1 and is fixed in r1p2. The workaround is to
set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Change-Id: Idadd323e419739fe909b9b68ea2dbe857846666b
Diffstat (limited to 'lib/cpus/aarch64/cortex_x3.S')
| -rw-r--r-- | lib/cpus/aarch64/cortex_x3.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index c781d3832..98d148e2e 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S @@ -42,6 +42,14 @@ workaround_reset_end cortex_x3, ERRATUM(2615812) check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) +workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 + /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ + sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 + sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 +workaround_reset_end cortex_x3, ERRATUM(2742421) + +check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) + workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 override_vector_table wa_cve_vbar_cortex_x3 |