diff options
| author | Govindraj Raja <govindraj.raja@arm.com> | 2023-04-24 15:21:19 -0500 |
|---|---|---|
| committer | Govindraj Raja <govindraj.raja@arm.com> | 2023-07-28 09:16:59 -0500 |
| commit | e48830712433e7562c053e46bc1d6e77982f58ca (patch) | |
| tree | c7ed5a632118c5c673c3bb93b7b30dfc6e966c42 /lib/cpus/aarch64/cortex_chaberton.S | |
| parent | af704705c135f85b8b1eeda938e3dcdba3f6e561 (diff) | |
refactor(cpus): use cpu errata wrappers for aarch64 hunter based cpus
Adapt to use errata frame-work cpu macro helpers for following cpus:
- cortex-a520
- cortex-a720
- cortex-x4
- cortex-chaberton
- cortex-blackhawk
- Use sysreg_bit_set helper macro for enabling of any system register
bit field.
- Use errata_report_shim macro for reporting errata.
- Use cpu_reset_func_start/end helpers for adding cpu reset functions.
Testing:
- Manual comparison of disassembly with and without conversion.
- Using the test script in gerrit - 19136
- Building with erratas and stepping through from ArmDS and running tftf.
Change-Id: I954fb603aa3746e02f2288656b98148d9cfd7843
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Diffstat (limited to 'lib/cpus/aarch64/cortex_chaberton.S')
| -rw-r--r-- | lib/cpus/aarch64/cortex_chaberton.S | 19 |
1 files changed, 4 insertions, 15 deletions
diff --git a/lib/cpus/aarch64/cortex_chaberton.S b/lib/cpus/aarch64/cortex_chaberton.S index 2c47bd381..596fe4a6b 100644 --- a/lib/cpus/aarch64/cortex_chaberton.S +++ b/lib/cpus/aarch64/cortex_chaberton.S @@ -21,12 +21,10 @@ #error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif -func cortex_chaberton_reset_func +cpu_reset_func_start cortex_chaberton /* Disable speculative loads */ msr SSBS, xzr - isb - ret -endfunc cortex_chaberton_reset_func +cpu_reset_func_end cortex_chaberton /* ---------------------------------------------------- * HW will do the cache maintenance while powering down @@ -37,21 +35,12 @@ func cortex_chaberton_core_pwr_dwn * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_CHABERTON_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_CHABERTON_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_CHABERTON_CPUPWRCTLR_EL1, CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT isb ret endfunc cortex_chaberton_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Chaberton. Must follow AAPCS. - */ -func cortex_chaberton_errata_report - ret -endfunc cortex_chaberton_errata_report -#endif +errata_report_shim cortex_chaberton /* --------------------------------------------- * This function provides Cortex Chaberton specific |