diff options
| author | Govindraj Raja <govindraj.raja@arm.com> | 2023-06-15 15:34:38 -0500 |
|---|---|---|
| committer | Govindraj Raja <govindraj.raja@arm.com> | 2023-08-03 14:10:28 -0500 |
| commit | 91ba1a5edf1983c61455972e58287299bb53fc1b (patch) | |
| tree | da79964a20939b4083b9db4c7071cc0e314df5c7 /lib/cpus/aarch64/cortex_a76ae.S | |
| parent | c62d9c7d27cfe99e7b0fcb0630ccff7c067b43cf (diff) | |
refactor(cpus): convert the Cortex-A76AE to use cpu helpers
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I72627afd0e2f10fb754d5c0de137fc9714ed391f
Diffstat (limited to 'lib/cpus/aarch64/cortex_a76ae.S')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76ae.S | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index f98bb44eb..08a6ef912 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S @@ -33,8 +33,7 @@ workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 * The Cortex-A76ae generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_cortex_a76ae - msr vbar_el3, x0 + override_vector_table wa_cve_vbar_cortex_a76ae isb #endif /* IMAGE_BL31 */ workaround_reset_end cortex_a76ae, CVE(2022, 23960) @@ -49,13 +48,7 @@ errata_report_shim cortex_a76ae * ---------------------------------------------------- */ func cortex_a76ae_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK - msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK isb ret endfunc cortex_a76ae_core_pwr_dwn |