diff options
| author | John Tsichritzis <john.tsichritzis@arm.com> | 2019-03-19 17:20:52 +0000 |
|---|---|---|
| committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-05-03 14:23:55 +0100 |
| commit | 076b5f02e2747ef1b5a55f1c5d368df16f046b1c (patch) | |
| tree | 05101ba7422f28e7d8a9826300ad0a20b04086cc /lib/cpus/aarch64/cortex_a76ae.S | |
| parent | 9a25f98261c134e3af4c1610c4afc74b01201fa2 (diff) | |
Add compile-time errors for HW_ASSISTED_COHERENCY flag
This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660
The introduced changes are the following:
1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.
2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.
3) The neoverse_e1.S file has been added to the FVP sources.
Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'lib/cpus/aarch64/cortex_a76ae.S')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a76ae.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index 1ba8e9a7d..46e9450f2 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S @@ -8,6 +8,11 @@ #include <cortex_a76ae.h> #include <cpu_macros.S> +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- |