diff options
| author | Bipin Ravi <bipin.ravi@arm.com> | 2022-02-23 23:45:50 -0600 |
|---|---|---|
| committer | John Powell <john.powell@arm.com> | 2022-03-18 01:01:34 +0200 |
| commit | 9b2510b69de26cc7f571731b415f6dec82669b6c (patch) | |
| tree | 7e390dfaf479fdefd0432eb654d6fd2098acefe8 /lib/cpus/aarch64/cortex_a57.S | |
| parent | be9121fd311ff48c94f3d90fe7efcf84586119e4 (diff) | |
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
This patch applies CVE-2022-23960 workarounds for Cortex-A75,
Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements
the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery
hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to
enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3
is implemented for A57/A72 because some revisions are affected by both
CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace
SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details
of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c
Diffstat (limited to 'lib/cpus/aarch64/cortex_a57.S')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 4120f119e..3766ec769 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -520,6 +520,11 @@ func check_errata_cve_2022_23960 ret endfunc check_errata_cve_2022_23960 +func check_smccc_arch_workaround_3 + mov x0, #ERRATA_APPLIES + ret +endfunc check_smccc_arch_workaround_3 + /* ---------------------------------------------------- * The CPU Ops core power down function for Cortex-A57. * ---------------------------------------------------- @@ -676,5 +681,6 @@ declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ cortex_a57_reset_func, \ check_errata_cve_2017_5715, \ CPU_NO_EXTRA2_FUNC, \ + check_smccc_arch_workaround_3, \ cortex_a57_core_pwr_dwn, \ cortex_a57_cluster_pwr_dwn |