diff options
| author | Stephan Gerhold <stephan@gerhold.net> | 2023-03-19 20:30:58 +0100 |
|---|---|---|
| committer | Stephan Gerhold <stephan@gerhold.net> | 2023-08-10 09:28:52 +0200 |
| commit | c5c160cdddd1c365a447c1fcd148fabb9014cce0 (patch) | |
| tree | 529785fddb9d10a2d69a3c0d46a4b760af41d511 /lib/cpus/aarch32 | |
| parent | 2360d18bb5ec40841feced55a3fe4f344c752f29 (diff) | |
fix(cpus): flush L2 cache for Cortex-A7/12/15/17
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.
Fix this by adding the L2 cache flush similar to cortex_a53.S.
Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Diffstat (limited to 'lib/cpus/aarch32')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a12.S | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a15.S | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a17.S | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch32/cortex_a7.S | 4 |
4 files changed, 16 insertions, 0 deletions
diff --git a/lib/cpus/aarch32/cortex_a12.S b/lib/cpus/aarch32/cortex_a12.S index 089c08987..8eec27cb2 100644 --- a/lib/cpus/aarch32/cortex_a12.S +++ b/lib/cpus/aarch32/cortex_a12.S @@ -64,6 +64,10 @@ func cortex_a12_cluster_pwr_dwn bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a12_disable_smp diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index 01323f581..b41676d94 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S @@ -163,6 +163,10 @@ func cortex_a15_cluster_pwr_dwn bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a15_disable_smp diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S index 8d76ab276..18775708a 100644 --- a/lib/cpus/aarch32/cortex_a17.S +++ b/lib/cpus/aarch32/cortex_a17.S @@ -159,6 +159,10 @@ func cortex_a17_cluster_pwr_dwn bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a17_disable_smp diff --git a/lib/cpus/aarch32/cortex_a7.S b/lib/cpus/aarch32/cortex_a7.S index 71542d57d..4842ca63d 100644 --- a/lib/cpus/aarch32/cortex_a7.S +++ b/lib/cpus/aarch32/cortex_a7.S @@ -64,6 +64,10 @@ func cortex_a7_cluster_pwr_dwn bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a7_disable_smp |