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authorAmbroise Vincent <ambroise.vincent@arm.com>2019-03-04 16:56:26 +0000
committerAmbroise Vincent <ambroise.vincent@arm.com>2019-03-13 14:05:47 +0000
commit75a1ada95efa78e4133bdd947c64944005a8e5c2 (patch)
treeb5dd986ec920d6dbcb5fc2f350fcb14efb1bf392 /lib/cpus/aarch32
parentc48d02bade88b07fa7f43aa44e5217f68e5d047f (diff)
Cortex-A15: Implement workaround for errata 816470
Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'lib/cpus/aarch32')
-rw-r--r--lib/cpus/aarch32/cortex_a15.S24
1 files changed, 23 insertions, 1 deletions
diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S
index b6c61ab7f..8c3bbf41e 100644
--- a/lib/cpus/aarch32/cortex_a15.S
+++ b/lib/cpus/aarch32/cortex_a15.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,6 +29,13 @@ func cortex_a15_disable_smp
bic r0, #CORTEX_A15_ACTLR_SMP_BIT
stcopr r0, ACTLR
isb
+#if ERRATA_A15_816470
+ /*
+ * Invalidate any TLB address
+ */
+ mov r0, #0
+ stcopr r0, TLBIMVA
+#endif
dsb sy
bx lr
endfunc cortex_a15_disable_smp
@@ -41,6 +48,20 @@ func cortex_a15_enable_smp
bx lr
endfunc cortex_a15_enable_smp
+ /* ----------------------------------------------------
+ * Errata Workaround for Cortex A15 Errata #816470.
+ * This applies only to revision >= r3p0 of Cortex A15.
+ * ----------------------------------------------------
+ */
+func check_errata_816470
+ /*
+ * Even though this is only needed for revision >= r3p0, it is always
+ * applied because of the low cost of the workaround.
+ */
+ mov r0, #ERRATA_APPLIES
+ bx lr
+endfunc check_errata_816470
+
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES
@@ -64,6 +85,7 @@ func cortex_a15_errata_report
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
+ report_errata ERRATA_A15_816470, cortex_a15, 816470
report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715
pop {r12, lr}