diff options
| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-02-18 16:55:43 +0000 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2019-02-18 17:03:16 +0000 |
| commit | ed4fc6f026999daad19b4bb47e6b6626078206c2 (patch) | |
| tree | 66a71202b0a92fae01a1e2b10c69235a5f358a72 /include/arch/aarch32/el3_common_macros.S | |
| parent | fa233ac9d435905d2717a9880cfb3a1671e37134 (diff) | |
Disable processor Cycle Counting in Secure state
In a system with ARMv8.5-PMU implemented:
- If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
in Secure state in PMCCNTR.
- If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
Secure state in PMCCNTR_EL0.
So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
as any EL can change that value.
Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'include/arch/aarch32/el3_common_macros.S')
| -rw-r--r-- | include/arch/aarch32/el3_common_macros.S | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 048f16103..ab9ba6ed5 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,10 +103,15 @@ * Initialise SDCR, setting all the fields rather than relying on hw. * * SDCR.SPD: Disable AArch32 privileged debug. Debug exceptions from - * Secure EL1 are disabled. + * Secure EL1 are disabled. + * + * SDCR: Set to one so that cycle counting by PMCCNTR is prohibited in + * Secure state. This bit is RES0 in versions of the architecture + * earlier than ARMv8.5, setting it to 1 doesn't have any effect on + * them. * --------------------------------------------------------------------- */ - ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE)) + ldr r0, =(SDCR_RESET_VAL | SDCR_SPD(SDCR_SPD_DISABLE) | SDCR_SCCD_BIT) stcopr r0, SDCR #endif |