diff options
| author | Javier Almansa Sobrino <javier.almansasobrino@arm.com> | 2020-11-23 18:38:15 +0000 |
|---|---|---|
| committer | Javier Almansa Sobrino <javier.almansasobrino@arm.com> | 2020-12-11 12:49:20 +0000 |
| commit | 0063dd1708e67e5d36168caaf2a0df383bbe1455 (patch) | |
| tree | d6297557e50a6c6c4672f78b37efa649f4439c74 /include/arch/aarch32/el3_common_macros.S | |
| parent | 852e494075d92199e9bddfe92d364f2107a5a25d (diff) | |
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.
If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.
This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
Diffstat (limited to 'include/arch/aarch32/el3_common_macros.S')
| -rw-r--r-- | include/arch/aarch32/el3_common_macros.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 4fd746d5a..580dd95b7 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -242,6 +242,10 @@ cps #MODE32_mon isb +#if DISABLE_MTPMU + bl mtpmu_disable +#endif + .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets. |