Merge changes from topic "stm32mp2" into integration

* changes:
  feat(stm32mp2): generate stm32 file
  feat(stm32mp2-fdts): add stm32mp257f-ev1 board
  feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files
  feat(stm32mp2-fdts): introduce stm32mp25 SoCs family
  feat(stm32mp2): add console configuration
  feat(st): add RCC registers list
  feat(st-uart): add AARCH64 stm32_console driver
  feat(st): introduce new platform STM32MP2
  feat(dt-bindings): add the STM32MP2 clock and reset bindings
  docs(changelog): add scopes for STM32MP2
  feat(docs): introduce STM32MP2 doc
  refactor(docs): add a sub-menu for ST platforms
  refactor(st): move plat_image_load.c
  refactor(st): rename PLAT_NB_FIXED_REGS
  refactor(st): move some storage definitions to common part
  refactor(st): move SDMMC definitions to driver
  feat(st-clock): stub fdt_get_rcc_secure_state
  feat(st-clock): allow aarch64 compilation of STGEN functions
  feat(st): allow AARCH64 compilation for common code
  refactor(st): rename QSPI macros

7 files changed, 453 insertions, 278 deletions

diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 026a463ff..447d10873 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -789,6 +789,7 @@ STM32MP1 platform port
 ^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Yann Gautier <yann.gautier@st.com>
 :|G|: `Yann-lms`_
+:|F|: docs/plat/st/*
 :|F|: docs/plat/stm32mp1.rst
 :|F|: drivers/st/
 :|F|: fdts/stm32\*
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 2eec68cf9..7a05fb649 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -42,7 +42,7 @@ Platform Ports
    rockchip
    socionext-uniphier
    synquacer
-   stm32mp1
+   st/index
    ti-k3
    xilinx-versal-net
    xilinx-versal
diff --git a/docs/plat/st/index.rst b/docs/plat/st/index.rst
new file mode 100644
index 000000000..95ec3d252
--- /dev/null
+++ b/docs/plat/st/index.rst
@@ -0,0 +1,14 @@
+STMicroelectronics STM32 MPUs
+=============================
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+
+   stm32mpus
+   stm32mp1
+   stm32mp2
+
+--------------
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mp1.rst b/docs/plat/st/stm32mp1.rst
new file mode 100644
index 000000000..35e8f8c7a
--- /dev/null
+++ b/docs/plat/st/stm32mp1.rst
@@ -0,0 +1,219 @@
+STM32MP1
+========
+
+STM32MP1 is a microprocessor designed by STMicroelectronics
+based on Arm Cortex-A7.
+It is an Armv7-A platform, using dedicated code from TF-A.
+More information can be found on `STM32MP1 Series`_ page.
+
+For TF-A common configuration of STM32 MPUs, please check
+:ref:`STM32 MPUs` page.
+
+STM32MP1 Versions
+-----------------
+
+There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
+
+STM32MP13 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP131: Single Cortex-A7 core
+- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
+- STM32MP135: STM32MP133 + DCMIPP, LTDC
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A      Cortex-A7 @ 650 MHz
+- C      Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
+- D      Cortex-A7 @ 900 MHz
+- F      Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
+
+STM32MP15 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
+- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
+- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A      Basic + Cortex-A7 @ 650 MHz
+- C      Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
+- D      Basic + Cortex-A7 @ 800 MHz
+- F      Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
+
+The `STM32MP1 part number codification`_ page gives more information about part numbers.
+
+Memory mapping
+--------------
+
+::
+
+    0x00000000 +-----------------+
+               |                 |   ROM
+    0x00020000 +-----------------+
+               |                 |
+               |       ...       |
+               |                 |
+    0x2FFC0000 +-----------------+ \
+               |     BL32 DTB    | |
+    0x2FFC5000 +-----------------+ |
+               |       BL32      | |
+    0x2FFDF000 +-----------------+ |
+               |       ...       | |
+    0x2FFE3000 +-----------------+ |
+               |     BL2 DTB     | | Embedded SRAM
+    0x2FFEA000 +-----------------+ |
+               |       BL2       | |
+    0x2FFFF000 +-----------------+ |
+               |  SCMI mailbox   | |
+    0x30000000 +-----------------+ /
+               |                 |
+               |       ...       |
+               |                 |
+    0x40000000 +-----------------+
+               |                 |
+               |                 |   Devices
+               |                 |
+    0xC0000000 +-----------------+ \
+               |                 | |
+    0xC0100000 +-----------------+ |
+               |       BL33      | | Non-secure RAM (DDR)
+               |       ...       | |
+               |                 | |
+    0xFFFFFFFF +-----------------+ /
+
+
+Build Instructions
+------------------
+
+STM32MP1x specific flags
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Dedicated STM32MP1 flags:
+
+- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
+  | Default: 0
+- | ``STM32MP13``: to select STM32MP13 variant configuration.
+  | Default: 0
+- | ``STM32MP15``: to select STM32MP15 variant configuration.
+  | Default: 1
+
+
+Boot with FIP
+~~~~~~~~~~~~~
+You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.
+
+U-Boot
+______
+
+.. code:: bash
+
+    cd <u-boot_directory>
+    make stm32mp15_trusted_defconfig
+    make DEVICE_TREE=stm32mp157c-ev1 all
+
+OP-TEE (optional)
+_________________
+
+.. code:: bash
+
+    cd <optee_directory>
+    make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
+        CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
+
+
+TF-A BL32 (SP_min)
+__________________
+If you choose not to use OP-TEE, you can use TF-A SP_min.
+To build TF-A BL32, and its device tree file:
+
+.. code:: bash
+
+    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+        AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs
+
+TF-A BL2
+________
+To build TF-A BL2 with its STM32 header for SD-card boot:
+
+.. code:: bash
+
+    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+        DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
+
+For other boot devices, you have to replace STM32MP_SDMMC in the previous command
+with the desired device flag.
+
+This BL2 is independent of the BL32 used (SP_min or OP-TEE)
+
+
+FIP
+___
+With BL32 SP_min:
+
+.. code:: bash
+
+    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+        AARCH32_SP=sp_min \
+        DTB_FILE_NAME=stm32mp157c-ev1.dtb \
+        BL33=<u-boot_directory>/u-boot-nodtb.bin \
+        BL33_CFG=<u-boot_directory>/u-boot.dtb \
+        fip
+
+With OP-TEE:
+
+.. code:: bash
+
+    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
+        AARCH32_SP=optee \
+        DTB_FILE_NAME=stm32mp157c-ev1.dtb \
+        BL33=<u-boot_directory>/u-boot-nodtb.bin \
+        BL33_CFG=<u-boot_directory>/u-boot.dtb \
+        BL32=<optee_directory>/tee-header_v2.bin \
+        BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
+        BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin
+        fip
+
+Trusted Boot Board
+__________________
+
+.. code:: shell
+
+    tools/cert_create/cert_create -n --rot-key build/stm32mp1/release/rot_key.pem \
+        --tfw-nvctr 0 \
+        --ntfw-nvctr 0 \
+        --key-alg ecdsa --hash-alg sha256 \
+        --trusted-key-cert build/stm32mp1/release/trusted_key.crt \
+        --tos-fw <optee_directory>/tee-header_v2.bin \
+        --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
+        --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
+        --tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \
+        --tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \
+        --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
+        --nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \
+        --nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \
+        --hw-config <u-boot_directory>/u-boot.dtb \
+        --fw-config build/stm32mp1/release/fdts/fw-config.dtb \
+        --stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt
+
+    tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
+        --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
+        --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
+        --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
+        --hw-config <u-boot_directory>/u-boot.dtb \
+        --fw-config build/stm32mp1/release/fdts/fw-config.dtb \
+        --tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \
+        --tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \
+        --nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \
+        --nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \
+        --stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt \
+        build/stm32mp1/release/stm32mp1.fip
+
+
+.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
+.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
new file mode 100644
index 000000000..43e131d71
--- /dev/null
+++ b/docs/plat/st/stm32mp2.rst
@@ -0,0 +1,133 @@
+STM32MP2
+========
+
+STM32MP2 is a microprocessor designed by STMicroelectronics
+based on Arm Cortex-A35.
+
+For TF-A common configuration of STM32 MPUs, please check
+:ref:`STM32 MPUs` page.
+
+STM32MP2 Versions
+-----------------
+
+The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
+
+- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
+- STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI / NN - LVDS
+- STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS
+- STM32MP251: Single Cortex-A35 core, Cortex-M33 core - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A      Basic + Cortex-A35 @ 1GHz
+- C      Secure Boot + HW Crypto + Cortex-A35 @ 1GHz
+- D      Basic + Cortex-A35 @ 1.5GHz
+- F      Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+Memory mapping
+--------------
+
+::
+
+    0x00000000 +-----------------+
+               |                 |
+               |       ...       |
+               |                 |
+    0x0E000000 +-----------------+ \
+               |       BL31      | |
+               +-----------------+ |
+               |       ...       | |
+    0x0E012000 +-----------------+ |
+               |     BL2 DTB     | | Embedded SRAM
+    0x0E016000 +-----------------+ |
+               |       BL2       | |
+    0x0E040000 +-----------------+ /
+               |                 |
+               |       ...       |
+               |                 |
+    0x40000000 +-----------------+
+               |                 |
+               |                 |   Devices
+               |                 |
+    0x80000000 +-----------------+ \
+               |                 | |
+               |                 | | Non-secure RAM (DDR)
+               |                 | |
+    0xFFFFFFFF +-----------------+ /
+
+
+Build Instructions
+------------------
+
+STM32MP2x specific flags
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Dedicated STM32MP2 build flags:
+
+- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
+  | Default: 1
+- | ``STM32MP25``: to select STM32MP25 variant configuration.
+  | Default: 1
+
+To compile the correct DDR driver, one flag must be set among:
+
+- | ``STM32MP_DDR3_TYPE``: to compile DDR3 driver and DT.
+  | Default: 0
+- | ``STM32MP_DDR4_TYPE``: to compile DDR4 driver and DT.
+  | Default: 0
+- | ``STM32MP_LPDDR4_TYPE``: to compile LpDDR4 driver and DT.
+  | Default: 0
+
+
+Boot with FIP
+~~~~~~~~~~~~~
+You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) before building FIP binary.
+
+U-Boot
+______
+
+.. code:: bash
+
+    cd <u-boot_directory>
+    make stm32mp25_defconfig
+    make DEVICE_TREE=stm32mp257f-ev1 all
+
+OP-TEE
+______
+
+.. code:: bash
+
+    cd <optee_directory>
+    make CROSS_COMPILE64=aarch64-none-elf- CROSS_COMPILE32=arm-none-eabi-
+        ARCH=arm PLATFORM=stm32mp2 \
+        CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts
+
+TF-A BL2 & BL31
+_______________
+To build TF-A BL2 with its STM32 header and BL31 for SD-card boot:
+
+.. code:: bash
+
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
+        STM32MP_DDR4_TYPE=1 SPD=opteed \
+        DTB_FILE_NAME=stm32mp257f-ev1.dtb STM32MP_SDMMC=1
+
+For other boot devices, you have to replace STM32MP_SDMMC in the previous command
+with the desired device flag.
+
+
+FIP
+___
+
+.. code:: bash
+
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \
+        STM32MP_DDR4_TYPE=1 SPD=opteed \
+        DTB_FILE_NAME=stm32mp257f-ev1.dtb \
+        BL33=<u-boot_directory>/u-boot-nodtb.bin \
+        BL33_CFG=<u-boot_directory>/u-boot.dtb \
+        BL32=<optee_directory>/tee-header_v2.bin \
+        BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
+        fip
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mpus.rst b/docs/plat/st/stm32mpus.rst
new file mode 100644
index 000000000..931dd57fe
--- /dev/null
+++ b/docs/plat/st/stm32mpus.rst
@@ -0,0 +1,78 @@
+STM32 MPUs
+==========
+
+STM32 MPUs are microprocessors designed by STMicroelectronics
+based on Arm Cortex-A. This page presents the common configuration of STM32
+MPUs, more details and dedicated configuration can be found in each STM32 MPU
+page (:ref:`STM32MP1` or :ref:`STM32MP2`)
+
+Design
+------
+The STM32 MPU resets in the ROM code of the Cortex-A.
+The primary boot core (core 0) executes the boot sequence while
+secondary boot core (core 1) is kept in a holding pen loop.
+The ROM code boot sequence loads the TF-A binary image from boot device
+to embedded SRAM.
+
+The TF-A image must be properly formatted with a STM32 header structure
+for ROM code is able to load this image.
+Tool stm32image can be used to prepend this header to the generated TF-A binary.
+
+Boot
+~~~~
+Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
+inside the FIP binary: BL31 (for Aarch64 platforms), BL32 (OP-TEE), U-Boot
+and their respective device tree blobs.
+
+Boot sequence
+~~~~~~~~~~~~~
+
+ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
+
+Build Instructions
+------------------
+Boot media(s) supported by BL2 must be specified in the build command.
+Available storage medias are:
+
+- ``STM32MP_SDMMC``
+- ``STM32MP_EMMC``
+- ``STM32MP_RAW_NAND``
+- ``STM32MP_SPI_NAND``
+- ``STM32MP_SPI_NOR``
+
+Serial boot devices:
+
+- ``STM32MP_UART_PROGRAMMER``
+- ``STM32MP_USB_PROGRAMMER``
+
+
+Other configuration flags:
+
+- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
+  | Default: stm32mp157c-ev1.dtb
+- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
+  | default location (end of the first 128MB) is used when absent
+- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
+  | Default: 0 (disabled)
+- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
+  | Default: 0 (disabled)
+- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
+  | Default: 115200
+
+
+Populate SD-card
+----------------
+
+Boot with FIP
+~~~~~~~~~~~~~
+The SD-card has to be formatted with GPT.
+It should contain at least those partitions:
+
+- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2)
+- fip (GUID 19d5df83-11b0-457b-be2c-7559c13142a5): which contains the FIP binary
+
+Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
+
+--------------
+
+*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index a9836062d..f2c8fd228 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -1,280 +1,10 @@
-STMicroelectronics STM32MP1
-===========================
+:orphan:
 
-STM32MP1 is a microprocessor designed by STMicroelectronics
-based on Arm Cortex-A7.
-It is an Armv7-A platform, using dedicated code from TF-A.
-More information can be found on `STM32MP1 Series`_ page.
+STMicroelectronics STM32MP1 (old page)
+======================================
 
+Please check :ref:`STM32 MPUs` page for generic information about
+STMicroelectronics STM32 microprocessors in TF-A, and :ref:`STM32MP1` page
+for specificities on STM32MP1x platforms.
 
-STM32MP1 Versions
------------------
-
-There are 2 variants for STM32MP1: STM32MP13 and STM32MP15
-
-STM32MP13 Versions
-~~~~~~~~~~~~~~~~~~
-The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:
-
-- STM32MP131: Single Cortex-A7 core
-- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-- STM32MP135: STM32MP133 + DCMIPP, LTDC
-
-Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
-
-- A      Cortex-A7 @ 650 MHz
-- C      Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
-- D      Cortex-A7 @ 900 MHz
-- F      Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz
-
-STM32MP15 Versions
-~~~~~~~~~~~~~~~~~~
-The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:
-
-- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
-- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
-- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
-
-Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
-
-- A      Basic + Cortex-A7 @ 650 MHz
-- C      Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
-- D      Basic + Cortex-A7 @ 800 MHz
-- F      Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
-
-The `STM32MP1 part number codification`_ page gives more information about part numbers.
-
-Design
-------
-The STM32MP1 resets in the ROM code of the Cortex-A7.
-The primary boot core (core 0) executes the boot sequence while
-secondary boot core (core 1) is kept in a holding pen loop.
-The ROM code boot sequence loads the TF-A binary image from boot device
-to embedded SRAM.
-
-The TF-A image must be properly formatted with a STM32 header structure
-for ROM code is able to load this image.
-Tool stm32image can be used to prepend this header to the generated TF-A binary.
-
-Boot with FIP
-~~~~~~~~~~~~~
-The use of FIP is now the recommended way to boot STM32MP1 platform.
-Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
-inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective
-device tree blobs.
-
-
-Memory mapping
-~~~~~~~~~~~~~~
-
-::
-
-    0x00000000 +-----------------+
-               |                 |   ROM
-    0x00020000 +-----------------+
-               |                 |
-               |       ...       |
-               |                 |
-    0x2FFC0000 +-----------------+ \
-               |     BL32 DTB    | |
-    0x2FFC5000 +-----------------+ |
-               |       BL32      | |
-    0x2FFDF000 +-----------------+ |
-               |       ...       | |
-    0x2FFE3000 +-----------------+ |
-               |     BL2 DTB     | | Embedded SRAM
-    0x2FFEA000 +-----------------+ |
-               |       BL2       | |
-    0x2FFFF000 +-----------------+ |
-               |  SCMI mailbox   | |
-    0x30000000 +-----------------+ /
-               |                 |
-               |       ...       |
-               |                 |
-    0x40000000 +-----------------+
-               |                 |
-               |                 |   Devices
-               |                 |
-    0xC0000000 +-----------------+ \
-               |                 | |
-    0xC0100000 +-----------------+ |
-               |       BL33      | | Non-secure RAM (DDR)
-               |       ...       | |
-               |                 | |
-    0xFFFFFFFF +-----------------+ /
-
-
-Boot sequence
-~~~~~~~~~~~~~
-
-ROM code -> BL2(compiled with RESET_TO_BL2) -> BL32(SP_min)-> BL33(U-Boot)
-
-or if Op-TEE is used:
-
-ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot)
-
-
-Build Instructions
-------------------
-Boot media(s) supported by BL2 must be specified in the build command.
-Available storage medias are:
-
-- ``STM32MP_SDMMC``
-- ``STM32MP_EMMC``
-- ``STM32MP_RAW_NAND``
-- ``STM32MP_SPI_NAND``
-- ``STM32MP_SPI_NOR``
-
-Serial boot devices:
-
-- ``STM32MP_UART_PROGRAMMER``
-- ``STM32MP_USB_PROGRAMMER``
-
-
-Other configuration flags:
-
-- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used.
-  | Default: stm32mp157c-ev1.dtb
-- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
-  | default location (end of the first 128MB) is used when absent
-- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
-  | Default: 0 (disabled)
-- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
-  | Default: 0 (disabled)
-- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
-  | Default: 115200
-- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter.
-  | Default: 0
-- | ``STM32MP13``: to select STM32MP13 variant configuration.
-  | Default: 0
-- | ``STM32MP15``: to select STM32MP15 variant configuration.
-  | Default: 1
-
-
-Boot with FIP
-~~~~~~~~~~~~~
-You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.
-
-U-Boot
-______
-
-.. code:: bash
-
-    cd <u-boot_directory>
-    make stm32mp15_trusted_defconfig
-    make DEVICE_TREE=stm32mp157c-ev1 all
-
-OP-TEE (optional)
-_________________
-
-.. code:: bash
-
-    cd <optee_directory>
-    make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \
-        CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts
-
-
-TF-A BL32 (SP_min)
-__________________
-If you choose not to use OP-TEE, you can use TF-A SP_min.
-To build TF-A BL32, and its device tree file:
-
-.. code:: bash
-
-    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
-        AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs
-
-TF-A BL2
-________
-To build TF-A BL2 with its STM32 header for SD-card boot:
-
-.. code:: bash
-
-    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
-        DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1
-
-For other boot devices, you have to replace STM32MP_SDMMC in the previous command
-with the desired device flag.
-
-This BL2 is independent of the BL32 used (SP_min or OP-TEE)
-
-
-FIP
-___
-With BL32 SP_min:
-
-.. code:: bash
-
-    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
-        AARCH32_SP=sp_min \
-        DTB_FILE_NAME=stm32mp157c-ev1.dtb \
-        BL33=<u-boot_directory>/u-boot-nodtb.bin \
-        BL33_CFG=<u-boot_directory>/u-boot.dtb \
-        fip
-
-With OP-TEE:
-
-.. code:: bash
-
-    make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \
-        AARCH32_SP=optee \
-        DTB_FILE_NAME=stm32mp157c-ev1.dtb \
-        BL33=<u-boot_directory>/u-boot-nodtb.bin \
-        BL33_CFG=<u-boot_directory>/u-boot.dtb \
-        BL32=<optee_directory>/tee-header_v2.bin \
-        BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
-        BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin
-        fip
-
-Trusted Boot Board
-__________________
-
-.. code:: shell
-
-    tools/cert_create/cert_create -n --rot-key "build/stm32mp1/debug/rot_key.pem" \
-        --tfw-nvctr 0 \
-        --ntfw-nvctr 0 \
-        --key-alg ecdsa --hash-alg sha256 \
-        --trusted-key-cert build/stm32mp1/cert_images/trusted-key-cert.key-crt \
-        --tos-fw <optee_directory>/tee-header_v2.bin \
-        --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
-        --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
-        --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
-        --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
-        --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
-        --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
-        --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
-        --hw-config <u-boot_directory>/u-boot.dtb \
-        --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
-        --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt
-
-    tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \
-        --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \
-        --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \
-        --nt-fw <u-boot_directory>/u-boot-nodtb.bin \
-        --hw-config <u-boot_directory>/u-boot.dtb \
-        --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \
-        --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \
-        --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \
-        --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \
-        --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \
-        --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip
-
-
-
-Populate SD-card
-----------------
-
-Boot with FIP
-~~~~~~~~~~~~~
-The SD-card has to be formatted with GPT.
-It should contain at least those partitions:
-
-- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2)
-- fip: which contains the FIP binary
-
-Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl.
-
-
-.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
-.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification
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