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| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-09-18 16:34:13 -0500 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2023-09-18 17:42:07 -0500 |
| commit | 8852fb5b7d94229475446c81cfa58851bc2204ff (patch) | |
| tree | aee7e8579db41bdca6ec3c97834d810b22ef5eea /docs | |
| parent | 88b2d81345dfd84902aae586a743d00ac5df2f48 (diff) | |
fix(cpus): workaround for Neoverse V2 erratum 2331132
Neoverse V2 erratum 2331132 is a Cat B erratum that applies to all
revisions <= r0p2 and is still open. The workaround is to write the
value 4'b1001 to the PF_MODE bits in the IMP_CPUECTLR2_EL1 register
which will place the data prefetcher in the most conservative mode
instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2332927/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ic6c76375df465a4ad2e20dd7add7037477d973c1
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 69d372259..283957bc7 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -523,6 +523,10 @@ For Neoverse V1, the following errata build flags are defined : For Neoverse V2, the following errata build flags are defined : +- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 + CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still + open. + - ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 CPU, this affects system configurations that do not use and ARM interconnect IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed |