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| author | Sona Mathew <sonarebecca.mathew@arm.com> | 2023-10-03 17:09:09 -0500 |
|---|---|---|
| committer | Sona Mathew <sonarebecca.mathew@arm.com> | 2023-10-04 13:45:16 -0500 |
| commit | 2454316c2ae4411d0071d88c3db3c95598f12498 (patch) | |
| tree | d0ca3c8c17905495cbc2a481f6b623f224597a79 /docs | |
| parent | 18b47a9ca4597091fbb62203fd107b52d65ac93b (diff) | |
fix(cpus): workaround for Cortex-X3 erratum 2070301
Cortex-X3 erratum 2070301 is a Cat B erratum that applies to all
revisions <= r1p2 and is still open.
The workaround is to write the value 4'b1001 to the PF_MODE bits
in the IMP_CPUECTLR2_EL1 register. This places the data prefetcher
in the most conservative mode instead of disabling it.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I337c4c7bb9221715aaf973a55d0154e1c7555768
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index bf0455809..ad05a505a 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -726,6 +726,10 @@ For Cortex-X2, the following errata build flags are defined : For Cortex-X3, the following errata build flags are defined : +- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 + CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of + the CPU and is still open. + - ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it is fixed in r1p1. |