diff options
author | Chris Kay <chris.kay@arm.com> | 2022-09-29 14:36:53 +0100 |
---|---|---|
committer | Chris Kay <chris.kay@arm.com> | 2023-02-10 17:01:46 +0000 |
commit | f90fe02f061b8a203391e566682221396b656c6f (patch) | |
tree | 815a889990659625658677ff72cb201ede489206 /bl1/bl1.ld.S | |
parent | 966660ecd0c8a3d6e4d18a5352bb431e71a9a793 (diff) |
style: normalize linker script code style
There are a variety of code styles used by the various linker scripts
around the code-base. This change brings them in line with one another
and attempts to make the scripts more friendly for skim-readers.
Change-Id: Ibee2afad0d543129c9ba5a8a22e3ec17d77e36ea
Signed-off-by: Chris Kay <chris.kay@arm.com>
Diffstat (limited to 'bl1/bl1.ld.S')
-rw-r--r-- | bl1/bl1.ld.S | 71 |
1 files changed, 41 insertions, 30 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index c4ec5fe25..124358cbb 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -5,9 +5,8 @@ */ /* - * The .data section gets copied from ROM to RAM at runtime. - * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes - * aligned regions in it. + * The .data section gets copied from ROM to RAM at runtime. Its LMA should be + * 16-byte aligned to allow efficient copying of 16-bytes aligned regions in it. * Its VMA must be page-aligned as it marks the first read/write page. */ #define DATA_ALIGN 16 @@ -24,23 +23,26 @@ MEMORY { RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE } -SECTIONS -{ +SECTIONS { . = BL1_RO_BASE; + ASSERT(. == ALIGN(PAGE_SIZE), - "BL1_RO_BASE address is not aligned on a page boundary.") + "BL1_RO_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA .text . : { __TEXT_START__ = .; + *bl1_entrypoint.o(.text*) *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) + . = ALIGN(PAGE_SIZE); + __TEXT_END__ = .; } >ROM - /* .ARM.extab and .ARM.exidx are only added because Clang need them */ + /* .ARM.extab and .ARM.exidx are only added because Clang needs them */ .ARM.extab . : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >ROM @@ -51,51 +53,57 @@ SECTIONS .rodata . : { __RODATA_START__ = .; + *(SORT_BY_ALIGNMENT(.rodata*)) - RODATA_COMMON + RODATA_COMMON /* * No need to pad out the .rodata section to a page boundary. Next is * the .data section, which can mapped in ROM with the same memory * attributes as the .rodata section. * - * Pad out to 16 bytes though as .data section needs to be 16 byte - * aligned and lld does not align the LMA to the aligment specified + * Pad out to 16 bytes though as .data section needs to be 16-byte + * aligned and lld does not align the LMA to the alignment specified * on the .data section. */ __RODATA_END__ = .; - . = ALIGN(16); + + . = ALIGN(16); } >ROM -#else +#else /* SEPARATE_CODE_AND_RODATA */ ro . : { __RO_START__ = .; + *bl1_entrypoint.o(.text*) *(SORT_BY_ALIGNMENT(.text*)) *(SORT_BY_ALIGNMENT(.rodata*)) - RODATA_COMMON + RODATA_COMMON *(.vectors) + __RO_END__ = .; /* - * Pad out to 16 bytes as .data section needs to be 16 byte aligned and - * lld does not align the LMA to the aligment specified on the .data - * section. + * Pad out to 16 bytes as the .data section needs to be 16-byte aligned + * and lld does not align the LMA to the alignment specified on the + * .data section. */ - . = ALIGN(16); + . = ALIGN(16); } >ROM -#endif +#endif /* SEPARATE_CODE_AND_RODATA */ ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, - "cpu_ops not defined for this platform.") + "cpu_ops not defined for this platform.") . = BL1_RW_BASE; + ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), - "BL1_RW_BASE address is not aligned on a page boundary.") + "BL1_RW_BASE address is not aligned on a page boundary.") DATA_SECTION >RAM AT>ROM + __DATA_RAM_START__ = __DATA_START__; __DATA_RAM_END__ = __DATA_END__; @@ -105,24 +113,26 @@ SECTIONS #if USE_COHERENT_MEM /* - * The base address of the coherent memory section must be page-aligned (4K) - * to guarantee that the coherent data are stored on their own pages and - * are not mixed with normal data. This is required to set up the correct - * memory attributes for the coherent data page tables. + * The base address of the coherent memory section must be page-aligned to + * guarantee that the coherent data are stored on their own pages and are + * not mixed with normal data. This is required to set up the correct memory + * attributes for the coherent data page tables. */ coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; + /* - * Memory page(s) mapped to this section will be marked - * as device memory. No other unexpected data must creep in. - * Ensure the rest of the current memory page is unused. + * Memory page(s) mapped to this section will be marked as device + * memory. No other unexpected data must creep in. Ensure the rest of + * the current memory page is unused. */ . = ALIGN(PAGE_SIZE); + __COHERENT_RAM_END__ = .; } >RAM -#endif +#endif /* USE_COHERENT_MEM */ __BL1_RAM_START__ = ADDR(.data); __BL1_RAM_END__ = .; @@ -135,15 +145,16 @@ SECTIONS * of BL1's actual content in Trusted ROM. */ __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; + ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, - "BL1's ROM content has exceeded its limit.") + "BL1's ROM content has exceeded its limit.") __BSS_SIZE__ = SIZEOF(.bss); #if USE_COHERENT_MEM __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; -#endif +#endif /* USE_COHERENT_MEM */ ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") } |