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authorHarrison Mutai <harrison.mutai@arm.com>2023-04-19 09:30:15 +0100
committerHarrison Mutai <harrison.mutai@arm.com>2023-05-12 14:38:22 +0100
commit5e7e8bfa4f6ea38d7f001fd1a4a1f266049241c8 (patch)
treeb6088062d7ea5da6e334a6eada80916bcfae261c /bl1/bl1.ld.S
parentaf5b49e992de76b9777d1bfa392fb4242c0ff823 (diff)
build(bl1): add symbols for memory layout
Add symbols for mapping the physical memory layout of BL1. There are symbols that partially satisfy this requirement, however, the naming of these is inconsistent. Change-Id: I615a7eb28d17e4c2983636ec021124de304573df Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Diffstat (limited to 'bl1/bl1.ld.S')
-rw-r--r--bl1/bl1.ld.S9
1 files changed, 8 insertions, 1 deletions
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index bec234b1e..a2527e63a 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,11 @@ MEMORY {
}
SECTIONS {
+ ROM_REGION_START = ORIGIN(ROM);
+ ROM_REGION_LENGTH = LENGTH(ROM);
+ RAM_REGION_START = ORIGIN(RAM);
+ RAM_REGION_LENGTH = LENGTH(RAM);
+
. = BL1_RO_BASE;
ASSERT(. == ALIGN(PAGE_SIZE),
@@ -97,6 +102,7 @@ SECTIONS {
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
"cpu_ops not defined for this platform.")
+ ROM_REGION_END = .;
. = BL1_RW_BASE;
ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
@@ -157,4 +163,5 @@ SECTIONS {
#endif /* USE_COHERENT_MEM */
ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
+ RAM_REGION_END = .;
}