diff options
| author | Manish Pandey <manish.pandey2@arm.com> | 2023-11-08 15:52:18 +0100 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-11-08 15:52:18 +0100 |
| commit | 9c473d888aac4fc83f88964c7f2e25dcc01fe236 (patch) | |
| tree | 089fb76be4535c4240bc1201ef24c73ec3cf4fa2 | |
| parent | 31a815db1aa08fe5df91f5059b81c563703c7816 (diff) | |
| parent | 655af4f49278476ebac6bb865e325eca865684f2 (diff) | |
Merge "fix(intel): update boot scratch cold register to use cold 8" into integration
| -rw-r--r-- | plat/intel/soc/common/socfpga_psci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c index 5ffd512ac..c93e13f52 100644 --- a/plat/intel/soc/common/socfpga_psci.c +++ b/plat/intel/soc/common/socfpga_psci.c @@ -62,7 +62,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr) #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 if (cpu_id == 0x00) { psci_boot = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)); - psci_boot |= 0x20000; /* bit 17 */ + psci_boot |= 0x80000; /* bit 19 */ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8), psci_boot); } |