diff options
| author | Kathleen Capella <kathleen.capella@arm.com> | 2022-07-22 16:26:36 -0400 |
|---|---|---|
| committer | Kathleen Capella <kathleen.capella@arm.com> | 2022-08-25 00:22:01 -0400 |
| commit | 14cddd7a58799c8a9d349a4adc0136c1ab5d0b6c (patch) | |
| tree | 7047669b70d067ad7fb018123f26ec4f065173b7 | |
| parent | 1631f9c75c6e9667a320c8daf6a05bb49b80826e (diff) | |
fix(gpt): correct the GPC enable sequence
Since GPC control register fields are permitted to be cached in a TLB,
invalidate TLB after setting fields to ensure future checks are using
the updated values.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I95630b40b673363bbf74da2705deca03089fff3a
| -rw-r--r-- | lib/gpt_rme/gpt_rme.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c index e001e5fde..a6e17a34d 100644 --- a/lib/gpt_rme/gpt_rme.c +++ b/lib/gpt_rme/gpt_rme.c @@ -693,10 +693,6 @@ int gpt_enable(void) return -EPERM; } - /* Invalidate any stale TLB entries */ - tlbipaallos(); - dsb(); - /* Write the base address of the L0 tables into GPTBR */ write_gptbr_el3(((gpt_config.plat_gpt_l0_base >> GPTBR_BADDR_VAL_SHIFT) >> GPTBR_BADDR_SHIFT) & GPTBR_BADDR_MASK); @@ -718,6 +714,15 @@ int gpt_enable(void) gpccr_el3 |= SET_GPCCR_ORGN(GPCCR_ORGN_WB_RA_WA); gpccr_el3 |= SET_GPCCR_IRGN(GPCCR_IRGN_WB_RA_WA); + /* Prepopulate GPCCR_EL3 but don't enable GPC yet */ + write_gpccr_el3(gpccr_el3); + isb(); + + /* Invalidate any stale TLB entries and any cached register fields */ + tlbipaallos(); + dsb(); + isb(); + /* Enable GPT */ gpccr_el3 |= GPCCR_GPC_BIT; |