diff options
| author | Bipin Ravi <bipin.ravi@arm.com> | 2023-10-17 07:55:55 -0500 |
|---|---|---|
| committer | laurenw-arm <lauren.wehrmeister@arm.com> | 2023-11-02 10:12:36 -0500 |
| commit | d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2 (patch) | |
| tree | a93e47fc9655b7f6e06a4645eb68a328f4db41f0 | |
| parent | 68085ad4827ac7daa39767d479d0565daa32cb47 (diff) | |
fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 4 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a710.S | 8 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 5 | ||||
| -rw-r--r-- | services/std_svc/errata_abi/errata_abi_main.c | 5 |
4 files changed, 20 insertions, 2 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 95497862f..11e799246 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -612,6 +612,10 @@ For Cortex-A710, the following errata build flags are defined : interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and is still open. +- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and + r2p1 of the CPU and is still open. + - ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index c618d986e..f3931d743 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -178,6 +178,14 @@ workaround_reset_end cortex_a710, ERRATUM(2371105) check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) +workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 + /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ + sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) + sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) +workaround_reset_end cortex_a710, ERRATUM(2742423) + +check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) + workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 /* dsb before isb of power down sequence */ dsb sy diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 39e90cae5..8b167a8e8 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -607,6 +607,11 @@ CPU_FLAG_LIST += ERRATA_A710_2371105 # and is still open. CPU_FLAG_LIST += ERRATA_A710_2701952 +# Flag to apply erratum 2742423 workaround during reset. This erratum applies +# to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still +# open. +CPU_FLAG_LIST += ERRATA_A710_2742423 + # Flag to apply erratum 2768515 workaround during power down. This erratum # applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is # still open. diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c index f2ca0d135..108b8ff69 100644 --- a/services/std_svc/errata_abi/errata_abi_main.c +++ b/services/std_svc/errata_abi/errata_abi_main.c @@ -328,8 +328,9 @@ struct em_cpu_list cpu_list[] = { [13] = {2371105, 0x00, 0x20, ERRATA_A710_2371105}, [14] = {2701952, 0x00, 0x21, ERRATA_A710_2701952, \ ERRATA_NON_ARM_INTERCONNECT}, - [15] = {2768515, 0x00, 0x21, ERRATA_A710_2768515}, - [16 ... ERRATA_LIST_END] = UNDEF_ERRATA, + [15] = {2742423, 0x00, 0x21, ERRATA_A710_2742423}, + [16] = {2768515, 0x00, 0x21, ERRATA_A710_2768515}, + [17 ... ERRATA_LIST_END] = UNDEF_ERRATA, } }, #endif /* CORTEX_A710_H_INC */ |