diff options
| author | Chia-Wei Wang <chiawei_wang@aspeedtech.com> | 2023-10-30 09:14:53 +0800 |
|---|---|---|
| committer | Chia-Wei Wang <chiawei_wang@aspeedtech.com> | 2023-10-30 11:30:03 +0200 |
| commit | cef2e92568045da4e1d26a9ebfb38b0176b4ec33 (patch) | |
| tree | 0abe9b3ee9f5b967843a66e03bee79dbcb6e660b | |
| parent | ed2d256a68c44bdcde54db66382854c4e191b9f1 (diff) | |
fix(ast2700): add device mapping for coherent memory
The coherent memory should be mapped as Device nGnRnE.
This fix adds the missing MMU attributes for coherent memory
if enabled.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I90b8de167c48f03392c9740f88f4b1e7b073a82d
| -rw-r--r-- | plat/aspeed/ast2700/plat_bl31_setup.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c index fde5dbbc6..92a48ff80 100644 --- a/plat/aspeed/ast2700/plat_bl31_setup.c +++ b/plat/aspeed/ast2700/plat_bl31_setup.c @@ -76,6 +76,12 @@ void bl31_plat_arch_setup(void) BL_END - BL_CODE_END, MT_RW_DATA | MT_SECURE); +#if USE_COHERENT_MEM + mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); |