diff options
| author | Juan Pablo Conde <juanpablo.conde@arm.com> | 2023-09-19 14:57:29 -0500 |
|---|---|---|
| committer | Juan Pablo Conde <juanpablo.conde@arm.com> | 2023-10-26 11:25:28 -0500 |
| commit | a0594add2e2661a1b1e1f392bf015687004197bb (patch) | |
| tree | 6b9f2415aa9da9f6aa7122d4dab7fc318ca07758 | |
| parent | 0e1dc0f2bc2b0ee9bef9aabbdd52dd42fe4d41b4 (diff) | |
feat(cpus): add support for Travis CPU
Adding basic CPU library code to support Travis CPU
Change-Id: I3c85e9fab409325d213978888a8f6d6949291258
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
| -rw-r--r-- | include/lib/cpus/aarch64/travis.h | 29 | ||||
| -rw-r--r-- | lib/cpus/aarch64/travis.S | 71 | ||||
| -rw-r--r-- | plat/arm/board/fvp/platform.mk | 3 |
3 files changed, 102 insertions, 1 deletions
diff --git a/include/lib/cpus/aarch64/travis.h b/include/lib/cpus/aarch64/travis.h new file mode 100644 index 000000000..a8a255673 --- /dev/null +++ b/include/lib/cpus/aarch64/travis.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRAVIS_H +#define TRAVIS_H + +#define TRAVIS_MIDR U(0x410FD8C0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +/******************************************************************************* + * SME Control registers + ******************************************************************************/ +#define TRAVIS_SVCRSM S0_3_C4_C2_3 +#define TRAVIS_SVCRZA S0_3_C4_C4_3 + +#endif /* TRAVIS_H */ diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S new file mode 100644 index 000000000..2abefe944 --- /dev/null +++ b/lib/cpus/aarch64/travis.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <travis.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Travis must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Travis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +cpu_reset_func_start travis + /* ---------------------------------------------------- + * Disable speculative loads + * ---------------------------------------------------- + */ + msr SSBS, xzr +cpu_reset_func_end travis + +func travis_core_pwr_dwn +#if ENABLE_SME_FOR_NS + /* --------------------------------------------------- + * Disable SME if enabled and supported + * --------------------------------------------------- + */ + mrs x0, ID_AA64PFR1_EL1 + ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \ + #ID_AA64PFR1_EL1_SME_WIDTH + cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED + b.eq 1f + msr TRAVIS_SVCRSM, xzr + msr TRAVIS_SVCRZA, xzr +1: +#endif + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set TRAVIS_IMP_CPUPWRCTLR_EL1, \ + TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + isb + ret +endfunc travis_core_pwr_dwn + +errata_report_shim travis + +.section .rodata.travis_regs, "aS" +travis_regs: /* The ASCII list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func travis_cpu_reg_dump + adr x6, travis_regs + mrs x8, TRAVIS_IMP_CPUECTLR_EL1 + ret +endfunc travis_cpu_reg_dump + +declare_cpu_ops travis, TRAVIS_MIDR, \ + travis_reset_func, \ + travis_core_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 165b1610b..dadfc0d84 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -216,7 +216,8 @@ else lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/cortex_x2.S \ lib/cpus/aarch64/cortex_gelas.S \ - lib/cpus/aarch64/nevis.S + lib/cpus/aarch64/nevis.S \ + lib/cpus/aarch64/travis.S endif # AArch64/AArch32 cores FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ |