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| author | Manish Pandey <manish.pandey2@arm.com> | 2023-11-01 19:41:38 +0100 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-11-01 19:41:38 +0100 |
| commit | 899bcc84581062bf583527d6a2652efc99f2b12e (patch) | |
| tree | 2ddf87ac5fe00ef9afac3db7ea322f2cd4bef5f5 | |
| parent | e712f92408947a5fea79f2f1e106823929dec8ca (diff) | |
| parent | 6bd79b13f8a8566d047ff25da9110a887b4e36e7 (diff) | |
Merge "fix(tegra): return correct error code for plat_core_pos_by_mpidr" into integration
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_setup.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index d6d090aba..b21faa361 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -302,14 +302,14 @@ int32_t plat_core_pos_by_mpidr(u_register_t mpidr) */ if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) || (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) { - ret = PSCI_E_NOT_PRESENT; + ret = -1; } else { /* calculate the core position */ pos = cpu_id + (cluster_id << 2U); /* check for non-existent CPUs */ if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) { - ret = PSCI_E_NOT_PRESENT; + ret = -1; } else { ret = (int32_t)pos; } |