diff options
| author | Harsimran Singh Tungal <harsimransingh.tungal@arm.com> | 2023-10-20 11:20:48 +0100 |
|---|---|---|
| committer | hartun01-arm <harsimransingh.tungal@arm.com> | 2023-10-31 23:00:31 +0100 |
| commit | 3ff5fc2b35638afea2fad3cd0c76dcadc1adb8c2 (patch) | |
| tree | c1c8806cb7b5d45974d4da2e6764dca8ae09322a | |
| parent | 5856a91a641a4cd7403143bb90b098855a77ac16 (diff) | |
fix(corstone-1000): modify boot device dependencies
Modify boot device dependencies and remove the one's
which are not needed.
Change-Id: I71cd60558ab4bb5162afefad4f00d631c2308e72
Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
| -rw-r--r-- | plat/arm/board/corstone1000/common/include/platform_def.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h index 584d485f3..442d187f0 100644 --- a/plat/arm/board/corstone1000/common/include/platform_def.h +++ b/plat/arm/board/corstone1000/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -173,16 +173,15 @@ /* NOR Flash */ -#define PLAT_ARM_BOOT_BANK_FLAG UL(0x08002000) -#define PLAT_ARM_FIP_BASE_BANK0 UL(0x081EF000) -#define PLAT_ARM_FIP_BASE_BANK1 UL(0x0916F000) -#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ - #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE #define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ - -#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE_BANK0 +#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ +#define PLAT_ARM_FLASH_IMAGE_BASE UL(0x08000000) #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE +#define PLAT_ARM_FIP_OFFSET_IN_GPT (0x86000) + +/* FIP Information */ +#define FIP_SIGNATURE_AREA_SIZE (0x1000) /* 4 KB */ /* * Some data must be aligned on the biggest cache line size in the platform. |