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authorMadhukar Pappireddy <madhukar.pappireddy@arm.com>2023-10-31 23:15:55 +0100
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2023-10-31 23:15:55 +0100
commit33bb5787416b4e52b6e53a21178fc4bd68b5ff07 (patch)
treedd8fdad1e5b9f84b91db4fc4afbcad1607111b58
parent956201137588c99483a36df5f3fbb3dedc45a2a0 (diff)
parent278beb894aeda23278a01c3c6aff1f40b8ce0a34 (diff)
Merge "feat(cpufeat): add memory retention bit define for CLUSTERPWRDN" into integration
-rw-r--r--include/arch/aarch32/arch.h1
-rw-r--r--include/arch/aarch64/arch.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index da4ee7f11..a7117532c 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -796,5 +796,6 @@
#define DSU_CLUSTER_PWR_OFF 0
#define DSU_CLUSTER_PWR_ON 1
#define DSU_CLUSTER_PWR_MASK U(1)
+#define DSU_CLUSTER_MEM_RET BIT(1)
#endif /* ARCH_H */
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 001fad5c2..13927bd50 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1416,6 +1416,7 @@
#define DSU_CLUSTER_PWR_OFF 0
#define DSU_CLUSTER_PWR_ON 1
#define DSU_CLUSTER_PWR_MASK U(1)
+#define DSU_CLUSTER_MEM_RET BIT(1)
/*******************************************************************************
* Definitions for CPU Power/Performance Management registers