From c8f6a6769694c1aed3ba01d649126168f4385eec Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Thu, 13 Jan 2022 13:44:53 +0000 Subject: feat(tftf): introduce handler for synchronous exceptions Introduce a handler for synchronous exceptions (for aarch64) which currently is treated as unhandled exception. Also, added the capability to allow registering a custom handler by tftf framework to allow graceful exit while doing negative tests. Signed-off-by: Olivier Deprez Signed-off-by: Manish Pandey Change-Id: I4d8d1f5af9951edfe8f068ce85f7d434b2ec070f --- include/lib/aarch64/sync.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/lib/aarch64/sync.h (limited to 'include/lib') diff --git a/include/lib/aarch64/sync.h b/include/lib/aarch64/sync.h new file mode 100644 index 0000000..5058980 --- /dev/null +++ b/include/lib/aarch64/sync.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SYNC_H__ +#define __SYNC_H__ + +typedef bool (*exception_handler_t)(void); +void register_custom_sync_exception_handler(exception_handler_t handler); +void unregister_custom_sync_exception_handler(void); + +#endif /* __SYNC_H__ */ -- cgit v1.2.3 From c61ce3a49f70c9c96f536fb963edff0e64bde8f2 Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Tue, 18 Jan 2022 15:51:49 +0100 Subject: tftf(arch): exception syndrome iss macro Add macros to extract the ISS portion of an ELx ESR exception syndrome register. Signed-off-by: Olivier Deprez Signed-off-by: Manish Pandey Change-Id: I2bc94f05858f2dcbbe8ba81362bf660324fd388d --- include/lib/aarch64/arch.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/lib') diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index d9bc33c..371a546 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -654,6 +654,8 @@ #define ESR_EC_SHIFT U(26) #define ESR_EC_MASK U(0x3f) #define ESR_EC_LENGTH U(6) +#define ESR_ISS_SHIFT U(0x0) +#define ESR_ISS_MASK U(0x1ffffff) #define EC_UNKNOWN U(0x0) #define EC_WFE_WFI U(0x1) #define EC_AARCH32_CP15_MRC_MCR U(0x3) @@ -680,6 +682,10 @@ #define EC_AARCH32_FP U(0x28) #define EC_AARCH64_FP U(0x2c) #define EC_SERROR U(0x2f) +/* Data Fault Status code, not all error codes listed */ +#define ISS_DFSC_MASK U(0x3f) +#define DFSC_EXT_DABORT U(0x10) +#define DFSC_GPF_DABORT U(0x28) /* * External Abort bit in Instruction and Data Aborts synchronous exception @@ -688,6 +694,7 @@ #define ESR_ISS_EABORT_EA_BIT U(9) #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) +#define ISS_BITS(x) (((x) >> ESR_ISS_SHIFT) & ESR_ISS_MASK) /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ #define RMR_RESET_REQUEST_SHIFT U(0x1) -- cgit v1.2.3