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2020-08-18Merge changes from topic "af/add_branch_protection_makefiles"Olivier Deprez
* changes: TFTF: Add ARMv8.5 BTI support in makefiles TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library TFTF: Add ARMv8.5 BTI support in assembler files TFTF: Add ARMv8.5 BTI-related definitions
2020-08-18TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 libraryAlexei Fedorov
This patch adds BTI-related changes in xlat_tables_v2 library which fully correspond to those in TF-A source tree. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I77f3ae7e9a365406ebb3edd500dbc71d3f07ecad
2020-08-18TFTF: Add ARMv8.5 BTI support in assembler filesAlexei Fedorov
This patch adds BTI support in assembler files which fully correspond to those in TF-A source tree. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: Ie6a7b248c967684c6b2b86b915f0499fe095bba3
2020-07-23TFTF: Fix Aarch32 zeromem() functionAlexei Fedorov
This patch fixes the following bugs in zeromem() Aarch32 variant: - Removed ASM_ASSERT for length parameter passed in R1 register. This is causing assertion in tftf_entrypoint() code ldr r0, =__BSS_START__ ldr r1, =__BSS_SIZE__ bl zeromem when __BSS_SIZE__ is not 4-byte aligned: 0x000000000000cced __BSS_SIZE__ = SIZEOF (.bss) - With ENABLE_ASSERTIONS = 0 for RELEASE builds and R1 not 4-bytes aligned zeromem() was writing 0 into all the memory in infinite z_loop, because of the code: z_loop: cmp r2, r0 beq z_end str r1, [r0], #4 b z_loop with R0 being increased by 4 on each step and R2 = R0 condition would never be met. - BLT instruction was used for 'unsigned int length' value in R1 changed to BLO. This patch also fixes BLO instruction bug in 'memcpy4()' and function itself is optimised. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I8128399681def8ba80241882e355c3ca2778605f
2020-07-04Add explicit barrier before sev() in tftf_send_event_common APIMadhukar Pappireddy
Consider the following scenario: If sev() gets reordered above the event->cnt+=inc operation in tftf_send_event_common() on core 0, and lets say core 1 is in wfe in tftf_wait_for_event, core 1 receives the event before the write to event->cnt from core 0 propagates to core 1. Later, core 1 wakes up, reads event->cnt, sees that it is 0 and goes back to wfe, thereby leading to hang. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I2e8a5ab7c220b02d5b637dc7cdf3562ca73dbfdc
2020-03-23cactus: add symbols relocation fixupOlivier Deprez
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ibde8aadecf6ae6c320d01ee2acab9c3c8db3859d
2020-03-19tftf: provide hvc conduit facilityOlivier Deprez
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3ad6e6767c2ca915f4a4fe8c5accc07e3e255387
2020-02-11Switch AARCH32/AARCH64 to __aarch64__Deepika Bhavnani
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) NOTE: This change is based on below TFA commit https://github.com/ARM-software/arm-trusted-firmware/commit/402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: If2c3dbaeb01d4a9d8cfd95d906e5eaf4ae94417f
2020-01-13Merge "Make TFTF RFC 4122 compliant"Sandrine Bailleux
2020-01-13Make TFTF RFC 4122 compliantOliver Swede
This is a TFTF backport of a change that makes TF RFC 4122-compliant by converting the stored format of UUIDs from machine order (little endian) to network order (big endian). This patch changes the data structure used to store the values in the same way as in the related change in TF: 033648652f2d66abe2454a75ded891a47cb13446. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I052e570b80de61f87a049a08e347a2e5da7f841b
2020-01-08TFTF: Enable ARMv8.3-PAuth in FWU tests.Alexei Fedorov
This patch adds ARMv8.3-PAuth support for FWU tests. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I36a0a2a3870db51cda0a09bd8fd8004e2d01d2bc
2019-11-21Support for extended register usage in SMCCC v1.2 specMadhukar Pappireddy
The new version of SMC Calling Convention spec makes X0-X7/W0-W7/R0-R7 registers available for returning results and X1-X7/W1-W7/R1-R7 for passing arguments during SMC calls. This patch makes necessary changes to support the update in register usage and also enhances existing test case to check for expected behavior across SMC call. Link to the SMCCC spec: https://developer.arm.com/docs/den0028/c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I9e5a3e4f9de388cb9a7426b0eae1c0fa1229292a
2019-10-04TF-A Tests: Enable PAuth on warm boot pathAlexei Fedorov
This patch provides the following features and makes modifications listed below: - `plat_init_apiakey()` function is replaced with `init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys. - Source file `pauth.c` moved from `plat/common/aarch64` to `lib/extensions/pauth/aarch64` folder which contains PAuth specific code. - Individual APIAKey key generation for each CPU on every warm boot. - Per-CPU storage of APIAKey added in `tftf_suspend_context` structure. - APIAKey key is saved/restored in arch context on entry/exit from suspended state. - Added `pauth_init_enable()` function which generates, programs and enables APIAKey in EL1/EL2. - Changes in documentation related to ARMv8.3-PAuth support. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: I964b8f964bb541cbb0b2f772cb0b07aed055fe36
2019-06-20libc: fix memchr implementationAmbroise Vincent
The previous implementation could behave incorrectly because of the sign extension of the char when compared to the int. Change-Id: Id1e40ca9cfb1c271cb391e26698862726b833c8b Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-06Cosmetic changes to suspend_private.hSandrine Bailleux
Reword some comments, express offsets relative to one another, move the compile-time assertions closer to the structure they depend on. Change-Id: Id3d61ca704321844d12c9bb25e2e6eb303a7a579 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-04-04xlat v2: Synchronize with TF-AAntonio Nino Diaz
Change-Id: Ibd277c918088cf2afdd262689fa1e1c4ad369619 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-03-04libc: Update includesAmbroise Vincent
Reflect the changes in the structure of libc. NB: the include of stdarg.h in nvm_results_helpers.c is not in alphabetical order because it needs to be included before stdio.h. Fixing this would require further changes. Change-Id: I07f62a3450802833408ff3e1f950fd3b643e5e33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-04libc: Adapt to TFTFAmbroise Vincent
Add support for functions used in TFTF but not in TF-A. Replaced calls to plat_panic_handler with calls to panic, since there is no implementation of the former in TFTF. Change-Id: Ic10de2c6e749db97b932cd7ffbb6067b5befe914 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-04libc: Delete stdlib filesAmbroise Vincent
Keep uuid, rand and strncpy for compatibility reasons Change-Id: Iefd82a5c9df48f6159732027e40a58f7d6afc09f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-04libc: Import from TF-AAmbroise Vincent
Based on arm-trusted-firware commit 873e394b3bf93214a441f9f98237b58fbbea55aa Change-Id: I510e092f2b9ff333e9461bdde8d80ed1fab1460c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-02-11Synchronize files with TF-A repositoryAntonio Nino Diaz
Change-Id: Ieb56d0639efd29c2695751b2b36cc98ce2c90dab Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-25Sanitise includes of include/drivers across codebaseAntonio Nino Diaz
Enforce full include path for includes. The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them with the same name). Change-Id: I45e912b16c9fff81f50840dad7e7f90ed6637b2a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-18Use lock-less printf() in assert macroSandrine Bailleux
This allows to use assertions in interrupt context (which we do in some places currently). Before this patch, a CPU could dead lock itself by: 1. acquiring the printf lock in the normal execution context; 2. taking an interrupt while still holding the lock; 3. inside the interrupt handler, executing an assertion check that fails and thus tries to print an error message on the UART. In a situation where several CPUs might be executing assert() at the same time, we will now get interleaved messages but that should be pretty rare. Change-Id: I6d1603300f6a3ea5756a46338cb950b7ca3e7956 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-14Add CFI debug info to vector entriesSandrine Bailleux
This is based on TF-A commit 31823b6961d35a5d53e81d3bf4977ad7b2be81dd. Add Call Frame Information assembler directives to vector entries so that debuggers display the backtrace of functions that triggered a synchronous exception. For example, a function triggering a data abort will be easier to debug if the backtrace can be displayed from a breakpoint at the beginning of the synchronous exception vector. DS-5 needs CFI otherwise it will not attempt to display the backtrace. Other debuggers might have other needs. These debug information are stored in the ELF file but not in the final binary. Change-Id: I1129419f318465049f53b5e41c304ea61fa44483 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-14Improve readability of exceptions stubs codeSandrine Bailleux
Change-Id: Ic9b90d7284b0bbde85fe3e31a025aab40360de03 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-11xlat v2: Dynamically detect need for CnP bitAntonio Nino Diaz
ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented in CPUs that don't implement all mandatory 8.2 features (and so have to claim to be a lower version). This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system ID registers to detect whether it is needed to set the bit or not. Change-Id: Ie818c1b91fc319f194d17e21da922798a2a76ec6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2019-01-07Make UUID buffer optional for is_trusted_os_present()Sandrine Bailleux
The caller might simply want to know whether there is a Trusted OS, without the need to identify it. Change-Id: I97eef8b6e6c4cb948d48735cd7170fced98aee9a Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2019-01-03Rename SMC first argumentSandrine Bailleux
'fid' (short for 'function ID') makes for a more explicit name. Change-Id: I41d90c39979162142b0377a68f4be90dc31de253 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-21Merge changes from topic "sb/terse-output"Sandrine Bailleux
* changes: Remove redundant error message in tftf_initialise_timer() Remove prints from VExpress NOR flash driver Remove prints in get_overall_test_result() Remove SHELL_COLOR build flag Do not print CPU MPID in mp_printf() Use vprintf() inside mp_printf() Add vprintf() in standard C library
2018-12-20Fix waitus()Sandrine Bailleux
waitus() was missing an instruction barrier before reading the system counter value. As a result, the CPU could speculatively read it and we would potentially base our delay loop on stale values. waitus() now uses the syscounter_read() helper function introduced in the previous patch, which has the required ISB. Change-Id: Ic37254485a9cdc4d4d2c86d245aa3273454e82ff Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-18Flush the UART before entering suspend modeSandrine Bailleux
Change-Id: I75fa2b864d9229950e53f5b8a46e8e6078d4780d Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-13Do not print CPU MPID in mp_printf()Sandrine Bailleux
mp_printf() should just be an MP-safe version of printf(), i.e. one that takes the console lock before printing. It should not be responsible for printing the CPU MPID as well, this decision should be left to the caller. Also make Cactus and Ivy use mp_printf(). Before that, they could not call this function because they couldn't access the MPIDR_EL1 as S-EL0 images. Change-Id: I4eafee01ffc279296395b94dd4a07cfbb8e858e2 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-13Use vprintf() inside mp_printf()Sandrine Bailleux
This avoid making an extra copy of the string buffer. Change-Id: Idd5d25741abed2a125669e0994f0a0f3e1f8ed4c Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-13Add vprintf() in standard C librarySandrine Bailleux
This is a trivial, unoptimised implementation. Change-Id: Ia05a3fbbc7582583f7e8ae06e464c96a6b4e766d Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-12-11SPM: Introduce SPRT C client libraryAntonio Nino Diaz
Change-Id: I2f110b4d06d2821d8bdf818ab7523a5c0a6b9ab9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-12-11lib/irq: Correct the spi_desc_table array indexChandni Cherukuri
The size of the spi_desc_table array is defined as 'PLAT_MAX_SPI_OFFSET_ID - MIN_SPI_ID' which causes out of bound access for SPI between 'PLAT_MAX_SPI_OFFSET_ID - MIN_SPI_ID' and 'PLAT_MAX_SPI_OFFSET_ID'. Define the correct size of spi_desc_table array as 'PLAT_MAX_SPI_OFFSET_ID + 1'. Change-Id: I32cc6fd1d63fa4a2e04387c8ce4b56f472f834ab Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2018-11-27Fix type of SMC function IDSandrine Bailleux
The SMC function identifier is always a 32-bit integer, regardless of the caller's execution state and of the SMC calling convention in use. Change-Id: I8d4f7b9efcea3f00ac2ff0a397ca0d8ab824eecb Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-11-26Remove unused AArch64 assembly helpersAntonio Nino Diaz
Change-Id: I55a567014023d593ec96dd9eff71bfca01db9c61 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-20xlat v2: Synchronise code with TFAntonio Nino Diaz
Change-Id: Ibf4fffbfc025b205223d17a579f8cde386252199 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-11-07Drop support for semihostingSandrine Bailleux
We don't use semihosting in any of our test configs at the moment so there's a risk this code might get broken without us notifying it. It seems better to reintroduce it if and when we actually need it. Change-Id: Iae84e3be034cc3da0248954aa5a1029ddd50aabb Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-10-10Trusted Firmware-A Tests, version 2.0Sandrine Bailleux
This is the first public version of the tests for the Trusted Firmware-A project. Please see the documentation provided in the source tree for more details. Change-Id: I6f3452046a1351ac94a71b3525c30a4ca8db7867 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: amobal01 <amol.balasokamble@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Co-authored-by: Asha R <asha.r@arm.com> Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Co-authored-by: David Cunado <david.cunado@arm.com> Co-authored-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: dp-arm <dimitris.papastamos@arm.com> Co-authored-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Co-authored-by: Jonathan Wright <jonathan.wright@arm.com> Co-authored-by: Kévin Petit <kevin.petit@arm.com> Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Co-authored-by: Sathees Balya <sathees.balya@arm.com> Co-authored-by: Shawon Roy <Shawon.Roy@arm.com> Co-authored-by: Soby Mathew <soby.mathew@arm.com> Co-authored-by: Thomas Abraham <thomas.abraham@arm.com> Co-authored-by: Vikram Kanigiri <vikram.kanigiri@arm.com> Co-authored-by: Yatharth Kochar <yatharth.kochar@arm.com>
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