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2023-09-08feat(rmm): modify rmi_realm_params structureAlexeiFedorov
This patch modifies rmi_realm_params structure according to definition of RmiRealmParams in RMM Specification 1.0-eac1. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I63c3097290004de90cd2222b24419aef517d9b49
2023-08-24refactor(fgt): modify FEAT_FGT test to check for init valuesJuan Pablo Conde
The original test checked only if FEAT_FGT was enabled. This new version of the test also checks whether the values of registers HFG*_EL2 are the values used during initialization. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I17673b813da7f14ef03349eead2c0a47cf3a8b26
2023-08-24feat(cpufeat): add feat detection helpersJuan Pablo Conde
This patch adds multiple feature detection helpers, useful for tests that need to check for the presence of those features. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: Ie6d39b9e9c8d28d0a4cd9d02350e2bedd016e45e
2023-08-03test: add discovery of el3 spmd logical partitionsRaghu Krishnamurthy
This patch adds a test to query the presence of an SPMD logical partition and also tests basic functionality using the ffa_partition_info_get_regs abi. Note that the register based discovery reports the presence of el3 spmd logical partitions whereas the memory based discovery interface does not report the el3 spmd logical partitions. To that end, the patch adds helper functions to use the register based discovery, and also refactors code that can be shared between the register and memory based interfaces. Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com> Change-Id: I755ffe4098c635de2c6aeb0ebe73eb16c3acd206
2023-08-03feat(ff-a): partition information via registersRaghu Krishnamurthy
This patch enables basic support for getting partition information via the ffa_partition_info_get_regs abi. This interface can be used to query partition information in the absence of rx/tx buffer or when using memory is inconvenient (such as early boot loaders etc). The patch adds the required calls, a few helper functions and enables the use of x8-x17 as return values, that is required for this abi to work. Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com> Change-Id: I70ed78e809a5bf77d77a49e5bc122c1989303ebb
2023-08-01Merge "fix(spm): stop spm from being built for in aarch32"Olivier Deprez
2023-07-31fix(spm): stop spm from being built for in aarch32Daniel Boulby
Hafnium does not support Aarch32 therefore we do not want to build in this case. Move spm related test helpers into their own file and add FF-A tests to the aarch32_tests_to_skip.txt file Signed-off-by: Daniel Boulby <daniel.boulby@arm.com> Change-Id: Ic5a83ddf4aae2b7dd4b1c30e4cc76b0447e5b405
2023-07-25test(tftf): test PAuth in RealmShruti Gupta
- Enable PAuth in Realm RL1 by default. - Check if PAuth keys are accessible in Realm RL1. - Check if Realm PAuth keys are preserved across RMM entry/exit. - Check if NS PAuth keys are preserved across RMM entry/exit. - Generate PAuth fault by cloberring LR. Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: I85d8e03ec604c96117555e7aa866453cb2745cfe
2023-06-13feat: introduce SError exception handlerManish Pandey
Introduce SError exception handler along with support to register a custom handler. The default behaviour is same as before if no handler is registered. This patch will allow tests to do a graceful exit after handling an SError. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Idbe37d3690e3a8e08fa3b0dff496d18d3022a8fc
2023-06-06feat(xlat): add support for 52 bit PA size with 4KB granularityJavier Almansa Sobrino
This patch adds support to the xlat library to for 52Bits of PA size with 4KB granularity (FEAT_LPA2). The patch only reports the right granularity when it supports FEAT_LPA2 and it does not enable the feature. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee0cab8e1f8844a6af135771d8f940ec7e1dce84
2023-05-24tftf(rme): check if RMM doesn't leak Realm contents in SVE registersArunachalam Ganapathy
This test verifies that the Realm contents in SVE registers are not seen by NS world once the Realm returns back to the host. This test performs the below steps: 1. Set NS world SVE VQ to max and write a known pattern. 2. Set NS world ZCR_EL2 with VQ as 0 (128 bits). 3. Create Realm with max SVE VQ 4. Call Realm to fill in Z registers 5. Once Realm returns, NS sets ZCR_EL2 with max VQ and reads the Z registers. 6. The upper bits of Z registers must be either 0 or the old values filled by NS world at step 1. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I8205190d1ce9c37b99d35cf5b15df21ca9b838c3
2023-05-24tftf(rme): intermittently switch to Realm while doing NS SVE opsArunachalam Ganapathy
Interleave NS SVE operations with Realm SVE operations and check whether SVE vectors are not affected. This test also configures SVE op array and SVE vector length with random value in NS and Realm for test each iteration. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I7a9ba4bd0d298f187baa3048ec622eb97ec3d99f
2023-05-24refactor(sve): move sve operations to a lib routineArunachalam Ganapathy
This patch moves the SVE subtract operation to a common sve library routine and takes a callback function that does the world switch while SVE operations are done in a loop. The callback is invoked after z0, z1 vectors are loaded and before the calculated results are stored back in the vector registers. This refactoring later helps to use this function to do context switch from NS to Secure world or from NS to Realm world based on the callback type. This patch also moves the SVE fill vector registers, read vector registers to a common sve library routine. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Iceb34b96fa85597be63a50c429ae0eb29f8fcaf8
2023-05-18feat(rme): add SVE Realm testsArunachalam Ganapathy
Verifies Realm with SVE support. Below tests are added - Check whether RMI features reports proper SVE VL - Create SVE Realm and check rdvl result - Create SVE Realm with invalid VL and check if it fails - Create SVE Realm and test ID registers - Create non SVE Realm and test ID registers - Create SVE Realm and probe all supported VLs - Check RMM preserves NS ZCR_EL2 register Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I98a20f34ce72c7c1a353ed13678870168fa27c48
2023-05-08Add tests for Errata management firmware interface.Sona Mathew
Add tests to confirm that the em_version, em_features and em_cpu_erratum_features calls conform to the errata abi spec. Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com> Change-Id: I8395026acc004a10d8c2c17ec689f4e0752143d8
2023-05-05fix(tftf) : add alignment to FPU state structureShruti Gupta
This patch adds 16 byte alignment to FPU structure. Without this change, the load/str instruction for FPU might fail depending on compiler. Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: If41f1625218c47f7801be80a3532ff782525d5ad
2023-05-05test(tftf): test FPU state registers context is preserved in RL/SE/NSShruti Gupta
Test that FPU/SIMD state are preserved during a randomly context switch between secure/non-secure/realm(R-EL1)worlds. FPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers, the test runs for 1000 iterations with random combination of: SECURE_FILL_FPU, SECURE_READ_FPU, REALM_FILL_FPU, REALM_READ_FPU, NONSECURE_FILL_FPU, NONSECURE_READ_FPU commands,to test all possible situations of synchronous context switch between worlds, while the content of those registers is being used. Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com> Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: I6da5fd334777000111924bb1239b77123a3dcea6
2023-05-05refactor(tftf): move SIMD/FPU save/restore routine to common libShruti Gupta
- Move FPU routines to common lib - FPU/SIMD state consist of the 32 SIMD vectors, FPCR and FPSR registers - Test that FPU/SIMD state are preserved during a context switch between secure/non-secure. Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: I88f0a9f716aafdd634c4eae5b885f839bb3deb00
2023-05-04Merge "refactor(rme): add helper macro for RME tests"Soby Mathew
2023-05-02Merge "feat(hcx): modified test to also check for reset value"Madhukar Pappireddy
2023-04-28feat(hcx): modified test to also check for reset valueJuan Pablo Conde
Previous test only checked for the presence of FEAT_HCX. However, as register HCRX_EL2 is initialized in EL3, the value read from it should be its reset value. As the test already existed, there is no new CI config. It can be run by using test group: tftf-l2-fvp/fvp-hcx-aarch64-only,fvp-hcx:fvp-tftf-fip.tftf-foundationv8 Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: I7fcd3d868fa4a7b4aee53fe3b141e8da1f670c0a
2023-04-28refactor(rme): add helper macro for RME testsArunachalam Ganapathy
This change adds SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP macro that checks if FEAT_RME is present and RMM is not TRP. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I100e713d8f4fce2826e60909580079834585fddb
2023-04-28feat(sme): add basic SME2 testsJayanth Dodderi Chidanand
FEAT_SME2 introduces an architectural register ZT0 to support lookup table feature. This patch ensures that EL3 has properly enabled the SME2 for use at lower exception levels, thereby disabling the traps execution at lower exception levels, when instructions access ZT0 register to EL3. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I46d51184b74c1e82c88344530601f2a3c1aee8ea
2023-04-28feat(sme): update sme/mortlach testsJayanth Dodderi Chidanand
FEAT_SME is an optional architectural extension from v9.2. Previously due to the lack of support in toolchain, testing SME instructions were overlooked and minimal tests were added. This patch addresses them, with additional tests to test the SME instructions. In order to avoid toolchain requirements we manually encode the instructions for accessing ZA array. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: Ia9edd2711d548757b96495498bf9d47b9db68a09
2023-04-24test(tftf): test Secure interrupt can preempt Realm EL1nabkah01
- Send a direct message request command to first Cactus SP to start the trusted watchdog timer. - Create and execute a busy loop to sleep the PE in the realm world for REALM_TIME_SLEEP ms. - Trusted watchdog timer expires during this time which leads to secure interrupt being triggered while cpu is executing in realm world. - Realm EL1 exits to host, but because the FIQ is still pending, the Host will be pre-empted to EL3. - Once the SP handles the interrupt, it returns execution back to normal world - TFTF parses REC's exit reason(FIQ in this case) - TFTF sends direct message request command to first Cactus SP to query last serviced interrupt and verifies it is Trusted watchdog interrupt. - TFTF disables watchdog and destroys Realm payload on exit. Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com> Change-Id: I6f4cfd334777000d33924bb1239b77182a3dcea6
2023-04-18refact(twdog): move trusted wdog API to spm_commonnabkah01
Other tests cases need same API to enable/disable twdog, so we need to move them to common place. Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com> Change-Id: Ie54cfdf44777000dda924bb1239b77182a3dced9
2023-04-13feat(ff-a): memory share bump to v1.1 EAC0J-Alves
Hafnium was updated to match FF-A v1.1 EAC0 [1]. This is the equivalent change for FF-A memory sharing tests. [1] https://review.trustedfirmware.org/c/hafnium/hafnium/+/15012 Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Ibf39ac35e1c7e336843be848fb389401dd792516
2023-04-05Merge "feat(memory share): FFA_FEATURES(FFA_MEM_RETRIEVE_REQ)"Olivier Deprez
2023-04-03feat(memory share): FFA_FEATURES(FFA_MEM_RETRIEVE_REQ)Karl Meakin
Updates tests to pass when built against https://review.trustedfirmware.org/c/hafnium/hafnium/+/18909 Signed-off-by: Karl Meakin <karl.meakin@arm.com> Change-Id: Ic6c39ca6916b9f9298d7668021963fec287b72c8
2023-04-01Merge "test(psci): add tests for OS-initiated mode"Joanna Farley
2023-03-31feat(rme): add PMU Realm testsAlexeiFedorov
This patch adds Realm PMU payload tests with PMU interrupt handling. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2
2023-03-23test(psci): add tests for OS-initiated modeWing Li
Change-Id: I33e135f659aea600f71e053ac3db57eb0172e22b Signed-off-by: Wing Li <wingers@google.com>
2023-01-26fix(ff-a): tftf handling of its RXTX buffer pairJ-Alves
The way tftf was handling the RXTX buffer pair created a dependency on a set of tests from 'test_ffa_setup_and_discovery.c'. This was problematic for test configurations for which the SPM tests are not present. This patch removes such dependency: - Delete the 'INIT_MAILBOX' macro, and 'init_mailbox' function; - RXTX buffer pair allocated within the 'get_tftf_mailbox'. They are mapped into the SPMC via FFA_RXTX_MAP, and are returned in the function's argument. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Ia010ebd21f11ab7ca6582b574ffc9179693b1eed
2022-12-16fix(tftf): align with RMM bet0 return codeAlexeiFedorov
Update test cases return codes according to RMM Bet0 Specification. These changes are based on https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/17892 This patch also fixes failure of 'Access from a SP to a Root region' tests when SPMC is not present. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I340f2b3bcee2b072f3874fd6a9f211b48ddf882b
2022-12-15Merge "feat(tftf): TFTF Realm extension enhancement"Soby Mathew
2022-12-07feat(tftf): TFTF Realm extension enhancementAlexeiFedorov
Adds randomisation of SMC RMI commands parameters and checking of X4-X7 return values as per SMCCC v1.2. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I7a332db873d2bd6cb400c5bf97ef0b8e9792b2d4
2022-12-06test(pmu): check if PMUv3 is functionalBoyan Karatotev
The PMU is tested for secure world leakage but there are no checks whether it works in the first place. The counter and event counters are exercised separately. This is because the functionality of one does not imply the functionality of the other (EL3 has separate controls for both). This additionally catches a corner case with FEAT_HPMN0 missing without failing all tests. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I966d3155cdd6edfde01af32f7c50c3bb3644274a
2022-12-06fix(pmu): extend PMEVTYPER.evtCount widthBoyan Karatotev
FEAT_PMUv3p1 extends this field from 10 to 16 bits. The upper bits are RES0 so backwards compatibility is preserved Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I98abb14bfe8e72f99318fe7d3e26420d91c1c55a
2022-12-06Merge "feat(spe): add support for more SPE versions"Madhukar Pappireddy
2022-11-28test(ff-a): check execution state property of partitionsKathleen Capella
FF-A Version 1.1 adds several additional flags to the properties field of the partition information descriptors. Test that execution state flag is set when FF-A v1.1 is specified and zero when FF-A v1.0 descriptors are being used. Currently only 64-bit execution state is supported for FF-A compliant partitions. Signed-off-by: Kathleen Capella <kathleen.capella@arm.com> Change-Id: Ice1b9a5a417e89cb26dd642be49348e8bfa282b9
2022-11-22refactor: remove deprecated spm libs and test codeOlivier Deprez
Remove references to former SPCI/SPRT implementation pre-dating now released FF-A specification. Remove the sample quark partition image based on those deprecated specifications. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I5b4e51457307c4ff5befd46132fd26d4ef21cdfa
2022-11-17feat(spe): add support for more SPE versionsManish V Badarkhe
From Armv8.8, more SPE versions are supported, such as FEAT_SPEv1p3 and FEAT_SPEv1p4. Included these versions in the test case. Also, moved enum and function to appropriate header. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I5d2999068e619aa5fdad104bbe0177dcedcd0d8c
2022-11-10Merge "feat: tftf realm extension"Soby Mathew
2022-11-09Merge "test(SMCCC): add test for SMCCC_ARCH_WORKAROUND_3"Manish V Badarkhe
2022-11-08feat: tftf realm extensionnabkah01
This patch adds Realm payload management capabilities to TFTF to act as a NS Host, it includes creation and destruction of a Realm, mapping of protected data and creation of all needed RTT levels, sharing of NS memory buffer from Host to Realm by mapping of unprotected IPA, create REC and auxiliary granules, exit Realm using RSI_HOST_CALL ABI. Older realm_payload name is used now for only R-EL1 test cases, RMI and SPM test cases have been moved to new file tests-rmi-spm. New TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk, as an offset from where R-EL1 payload memory resources start. Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com> Change-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7
2022-11-08refact(trng): cleanup TRNG service testsJayanth Dodderi Chidanand
This patch adds the following changes: 1. Updates tftf-docs on the TRNG test support 2. Improvise few other files and macro names Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I69bbcb24e8485d2cd1384970e7424541d11838af
2022-11-04test(SMCCC): add test for SMCCC_ARCH_WORKAROUND_3Bipin Ravi
This adds SMCCC tests for SMCCC_ARCH_WORKAROUND_3 applicable for Cortex-A57/72/73/75 introduced as part of CVE-2022-23960 mitigation. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: If56bb0a69deda9032e050bdd2de98c8c4a5becbb
2022-10-19test(sve): test SVE operations in NWdKathleen Capella
Test that SVE operations done in Normal world are unaffected by overlapping use of SIMD registers in Secure world. Signed-off-by: Kathleen Capella <kathleen.capella@arm.com> Change-Id: I2da5e6737e237974ddae87d9f766e7628478d899
2022-10-04test(interrupts): command to resume after managed exitMadhukar Pappireddy
This patch introduces a new command sent through direct request message to be used by an endpoint to allocate cpu cycles to resume a Cactus SP after managed exit. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: Iee3cca5c8db0a46048c14ed1c41d5af90a843c82
2022-10-04test(interrupts): hint fwd destination SP could be interruptedMadhukar Pappireddy
TFTF can send a hint to the destination SP to expect that the forwarded sleep command could be preempted by a non-secure interrupt. This can make the tests exercising SP's response to non-secure interrupt robust by allowing the destination SP to check if the forward destination SP has indeed been preempted. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I808ee6c63687438d0092a53389f11bf9b3dd532d
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