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2023-10-31feat(rmm-eac5): update RSI_VERSION, RMI_VERSIONShruti Gupta
This patch adds necessary support for RMI_VERSION and RSI_VERSION commands. Macro SMC_RSI_ABI_VERSION renamed to SMC_RSI_VERSION. Note. This patch sets both RSI and RMI version numbers to 1.0 as per RMM Specification 1.0-eac5. Signed-off-by: Shruti Gupta <shruti.gupta@arm.com> Change-Id: If4eb14d93f657388e2fe64ceefee002403cc4ae8
2023-07-31fix(spm): stop spm from being built for in aarch32Daniel Boulby
Hafnium does not support Aarch32 therefore we do not want to build in this case. Move spm related test helpers into their own file and add FF-A tests to the aarch32_tests_to_skip.txt file Signed-off-by: Daniel Boulby <daniel.boulby@arm.com> Change-Id: Ic5a83ddf4aae2b7dd4b1c30e4cc76b0447e5b405
2023-04-28refactor(rme): add helper macro for RME testsArunachalam Ganapathy
This change adds SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP macro that checks if FEAT_RME is present and RMM is not TRP. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I100e713d8f4fce2826e60909580079834585fddb
2023-04-28feat(sme): add basic SME2 testsJayanth Dodderi Chidanand
FEAT_SME2 introduces an architectural register ZT0 to support lookup table feature. This patch ensures that EL3 has properly enabled the SME2 for use at lower exception levels, thereby disabling the traps execution at lower exception levels, when instructions access ZT0 register to EL3. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I46d51184b74c1e82c88344530601f2a3c1aee8ea
2023-04-28feat(sme): update sme/mortlach testsJayanth Dodderi Chidanand
FEAT_SME is an optional architectural extension from v9.2. Previously due to the lack of support in toolchain, testing SME instructions were overlooked and minimal tests were added. This patch addresses them, with additional tests to test the SME instructions. In order to avoid toolchain requirements we manually encode the instructions for accessing ZA array. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: Ia9edd2711d548757b96495498bf9d47b9db68a09
2023-03-31feat(rme): add PMU Realm testsAlexeiFedorov
This patch adds Realm PMU payload tests with PMU interrupt handling. Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> Change-Id: I86ef96252e04c57db385e129227cc0d7dcd1fec2
2023-01-26fix(ff-a): tftf handling of its RXTX buffer pairJ-Alves
The way tftf was handling the RXTX buffer pair created a dependency on a set of tests from 'test_ffa_setup_and_discovery.c'. This was problematic for test configurations for which the SPM tests are not present. This patch removes such dependency: - Delete the 'INIT_MAILBOX' macro, and 'init_mailbox' function; - RXTX buffer pair allocated within the 'get_tftf_mailbox'. They are mapped into the SPMC via FFA_RXTX_MAP, and are returned in the function's argument. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Ia010ebd21f11ab7ca6582b574ffc9179693b1eed
2022-12-06test(pmu): check if PMUv3 is functionalBoyan Karatotev
The PMU is tested for secure world leakage but there are no checks whether it works in the first place. The counter and event counters are exercised separately. This is because the functionality of one does not imply the functionality of the other (EL3 has separate controls for both). This additionally catches a corner case with FEAT_HPMN0 missing without failing all tests. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I966d3155cdd6edfde01af32f7c50c3bb3644274a
2022-11-08feat: tftf realm extensionnabkah01
This patch adds Realm payload management capabilities to TFTF to act as a NS Host, it includes creation and destruction of a Realm, mapping of protected data and creation of all needed RTT levels, sharing of NS memory buffer from Host to Realm by mapping of unprotected IPA, create REC and auxiliary granules, exit Realm using RSI_HOST_CALL ABI. Older realm_payload name is used now for only R-EL1 test cases, RMI and SPM test cases have been moved to new file tests-rmi-spm. New TFTF_MAX_IMAGE_SIZE argument added to FVP platform.mk, as an offset from where R-EL1 payload memory resources start. Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com> Change-Id: Ida4cfd334795879d55924bb33b9b77182a3dcef7
2022-10-04fix(interrupts): dont enable virtual maintenance interruptsMadhukar Pappireddy
SPMC enables the following virtual maintenance interrupts by default for each Secure Partition: > MANAGED_EXIT_INTERRUPT_ID > NOTIFICATION_PENDING_INTERRUPT_INTID Hence, no need to send a request to SPs to enable them. Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I7fc605b9b78ad759728909cd28ad2d2083c5de54
2022-08-16feat(rng_trap): add tests for FEAT_RNG_TRAPJuan Pablo Conde
Added 2 tests that expect a trap to be triggered when a read is performed on: 1. RNDR register 2. RNDRRS register The result will be a panic signal and the whole system will halt, as there is no handler set for such trap. Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com> Change-Id: Ia979e60a106b394cc09dfdf94115354fb72142d1
2022-07-07feat(tftf): refactoring of some tftf function helpersnabkah01
This refactoring is introduced in order to reuse some useful function helpers which already exist in the code base, by moving one function to test_helpers.c Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com> Change-Id: If5c24da9062d100419220fe000409b73596e773c
2022-05-19test(spm): use ffa_helpers for ivy partitionDaniel Boulby
Allow the ivy partition to use the ffa_helpers functions. To achieve this we create a common struct for ff-a calls that is used for both parameters and returns, this aligns with the Hafnium implementation. We can then use preprocessor macros to pick either SMC or SVC as the conduit depending on the exception level the SP is running at. Change-Id: Ic9525baabcf40d15545b6f6d504cf954373f08f9 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2022-05-18Merge "feat(WFxT): add a test for WFxT instructions"Bipin Ravi
2022-05-18feat(ff-a): create function helper to setup FF-A mailboxnabkah01
Fix test dependencies issue when SPM test is used individually. Provide an API function from SPM test suite to initialize the FF-A mailbox and enable FF-A based message with SP. Signed-off-by: Nabil Kahlouche <nabil.kahlouche@arm.com> Change-Id: I246491907f1641c47937a9a1c91cfd4a9b8bfe20
2022-05-18feat(WFxT): add a test for WFxT instructionsManish V Badarkhe
This patch adds the test to verify the WFET and WFIT instructions introduced by FEAT_WFxT. WFET and WFIT instructions assist in generating local-timeout event and thereby act as wakeup event for the PE, when the virtual count in CNTVCT_EL0 (counter-timer virtual count) register equals or exceed the timeout value passed with these instructions. Accordingly, this testcase verifies whether the time lapsed matches the value supplied with WFET and WFIT instructions. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I9aea5da869db8520e305e49989cb71f166a582eb
2022-05-09feat(brbe): test that EL3 has properly enabled access to BRBEjohpow01
Access to FEAT_BRBE control registers must be explicitly enabled in EL3, this simple test just ensures that the registers are accessible or traps to EL3, similar to the TRBE test. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I0a25c5ce6beb6aa96b9428264b75cb3569ac535a
2022-03-25test(cactus): add test for NS memory sharing between SPsFederico Recanati
Define a new shared memory region in 48-bit address range (configured as NS in the TZC) in cactus-tertiary's manifest. Since SPs can share either secure or non-secure memory, propagate the security information in the relevant cactus commands: CACTUS_REQ_MEM_SEND_CMD and CACTUS_MEM_SEND_CMD. Change-Id: I10af24c96ff8fc0d13c80a52b0264a1482a5cf56 Signed-off-by: Federico Recanati <federico.recanati@arm.com>
2022-03-25fix(plat/arm/fvp): make address space configurableFederico Recanati
Make FVP physical/virtual address space sizes configurable, with default at 34-bit (previously hard-coded value). Maximum tested value is 48-bit, FVP interconnect doesn't yet support 52-bit PA. Increase MAX_XLAT_TABLE and consequently NS_BL1U_RW_SIZE and NS_BLU2_LIMIT to accommodate the increased translation tables (based on 48-bit max PA size). Custom PA size is passed to build system through the PA_SIZE define. FVP needs to be configured in a compatible way through the parameters: * cluster0.PA_SIZE, for each cluster; * bp.dram_size, setting a memory limit corresponding at least to PA_SIZE; * cci550.addr_width, interconnect address width should match PA_SIZE; * pci.pci_smmuv3.mmu.SMMU_IDR5, SMMU has to be configured as well if present. Change-Id: I57bc898fb2c9696c01fc8e20d00b4a3d09e22326 Signed-off-by: Federico Recanati <federico.recanati@arm.com>
2022-03-08fix(tftf): remove invalid_access test from standard testsManish Pandey
Invalid_access test suite performs negative tests by accessing invalid memory and catching it in custom exception handler. This test suite was made part of standard tests which is called for all platforms and each EL3 configuration. This test was failing for the case when EL3 was build with "HANDLE_EA_EL3_FIRST = 1" causing exceptions to be trapped in EL3 and not forwarded to EL2 to be handled by custom exception handler. To avoid this problem, remove this suite from standard test and introduce a new test configuration. This patch also fixes a minor compilation error in file cactus_test_memory_sharing.c Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I8a13617a01411be45c623dde2ccfc7d950f05f9a
2022-03-02Merge changes from topic "od/invalid-access-tests"Manish Pandey
* changes: test(tftf): prevent realm region access from nwd test(cactus): prevent realm region access from swd feat(fvp): enable test to access el3 memory feat(tftf): add tests to access invalid memory
2022-03-01Merge "test(el3-runtime): check DIT is retained on exception"Joanna Farley
2022-03-01feat(tftf): add tests to access invalid memoryManish Pandey
Add test framework to access memory addresses which are not accessible to tftf. The test only introduced for "aarch64" as there is no sync exception handler for "aarch32". The test framework will catch the error and do graceful exit. For now only test introduced is to access memory owned by EL3, which can be easily extended to add more tests to access realm/secure(in RME enabled systems). Platform needs to provide test address, if not then test will be skipped. Test steps: 1. Register a custom sync exception handler(try & catch) 2. Access a protected memory, should give data abort. 3. Exception handler should check if data abort then continue. 4. Unregister custom exception handler. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib8b199acb9b96548c889539610ff1b58777d3d1d
2022-02-02test(el3-runtime): check DIT is retained on exceptionDaniel Boulby
Add a test to check that the PSTATE bits not set in the Aarch64.TakeException but set to a default when taking an exception to EL3 are maintained after an exception and that changes in TSP do not effect the PSTATE in TFTF and vice versa. Signed-off-by: Daniel Boulby <daniel.boulby@arm.com> Change-Id: Id4d625c7e9cbb565ac236f844274319cc02c2335
2022-01-27feat(afp): add a test for Advanced floating-pointManish V Badarkhe
This test is to ensure that TFTF is allowed to write the FPCR register bits to control the floating-point operation when FEAT_AFP is implemented. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I21ea288e698bbe706aac55740e28d5f6ccb700dc
2021-11-10feat: spm helper functions for MP testsJ-Alves
Added two helper functions to help with SPM tests in a MP setup. - spm_core_sp_init: to initialize an SP in a given core. - get_current_core_id: to get the current core ID. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Iad10d43f258f5ed05ce52b87c94a9333c228f26d
2021-11-09refactor(spm): managed exit testsJ-Alves
Factored out code to enable managed exit interrupt for a given SP, to reuse it in the context of testing the Schedule Receiver Interrupt SWd behavior, in the context of notifications feature work. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Idcecd486c7a952f0842ebf90c274adcea9e30152
2021-11-09feat(cactus): count requests receivedJ-Alves
Message loop counts the amount of requests received in each core. The counting can be accessed through newly added test command CACTUS_GET_REQ_COUNT_CMD. Added such special command to be able to test delay Schedule Receiver Interrupt, in the context of the notifications feature. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Id0a5a9cf58e10d1221a1a0f0af6264474fe7e020
2021-10-29refactor(spm): helper functions for SPM's MP testsJ-Alves
Factored out code to power on cpus from direct messaging test, and placed in a helper function. To be used to test other multicore functionality. The function expects the cpu on handler to be implemented in the scope of the functionality to be tested. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: Ic0074dc85e0a906bae9d7b8cc071aff476f94de5
2021-08-26feat(sys_reg_trace): add trace system registers access testManish V Badarkhe
Added a test to read trace system registers to ensure that EL3 is giving permission to non-secure EL2 to access these registers. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I0bdbb5aff81a78fc3a3766278c48b25bb6e1779f
2021-08-26feat(trf): add trace filter control registers access testManish V Badarkhe
Added a test to read trace filter control registers to ensure that EL3 is giving permission to non-secure EL2 to access these registers. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I9354d8592bd187206add717b9d3b0206382a06d3
2021-08-26feat(trbe): add trace buffer control registers access testManish V Badarkhe
Added a test to read trace buffer control registers to ensure that EL3 is giving permission to non-secure EL2 to access these registers. Change-Id: I70faa5bb7e0bc648fbc3d14cb9c1b8da3470a201 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-09feat(ff-a): update FF-A version to v1.1Olivier Deprez
Bump the required FF-A version in framework and manifests to v1.1 as upstream feature development goes. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: If3dc227635f1c65d0623ed36ad7e3766c5d5e132
2021-06-30Merge "feat(sve): enable SVE tests in tftf"Olivier Deprez
2021-06-29feat(sve): enable SVE tests in tftfMax Shvetsov
Adding two tests to check that floating point context is preserved. 1. Use SIMD instructions on SVE-enabled system. 2. Use SVE instruction on a full-length vectors. Both tests check that floating point context is preserved after returning from the secure world. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: Idccff7c3f1658cc66b64e144cc00cda6e0aeea50
2021-06-18SPM: Add shim layer to Ivy partition and enable PIERuari Phipps
Add a shim layer that runs at S-EL1 to the Ivy partition. Also enable Ivy to be built with PIE. Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Signed-off-by: Daniel Boulby <daniel.boulby@arm.com> Change-Id: I821a8ac99d07200aec93ca29d182f8ab6716616c
2021-02-10[SPM] tidying common code to tftf and cactusMax Shvetsov
This patch moves the code used to test SPM functionality, not explicitly described in FF-A specification, from ffa_helpers to spm_common which is built for both tftf and cactus. Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I461efad977cc4d02701feea7b2215a61453716ef
2021-01-21Nit: Change name from helper function and macroJ-Alves
Removed reference to Hafnium in name from helper function and macro to make them generic. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I5bdba013b3a0478dc1ef9058e71747480ba5ff1d
2020-12-15TFTF: helpers for SPM testsJ-Alves
Added functions and macros to help check at the beginning of the test, that system is as expected for SPM tests in which Hafnium is deployed as SPMC. This includes: - Checking SPMC has expected FFA_VERSION; - Checking that expected FF-A endpoints are deployed in the system; - Getting global TFTF mailbox. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I9195bcff8ed93156e838b192bb70a9634e18fbbf
2020-12-10SPM: RXTX map test on TFTFJ-Alves
Some FF-A interfaces use RXTX buffers to exchange information with SPMC. To avoid repetition of RXTX mapping across the spm-related tests, and prevent allocation of multiple pages for RXTX buffers within TFTF runtime: - Implemented test helpers that hold address of RXTX buffers; - Implemented test to FFA_RXTX_MAP ABI, that also sets value of RXTX buffers; - Cleaned up memory sharing tests that previously implemented RXTX mapping. Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I4a67982d3d185bf83809156e4fce03c6edb967d9
2020-10-29SPM: TFTF skip test if FFA endpoint absentJ-Alves
Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I0f653ae7764ede3dda3e51bd4eb94b7025606203
2020-08-18Merge changes from topic "af/add_branch_protection_makefiles"Olivier Deprez
* changes: TFTF: Add ARMv8.5 BTI support in makefiles TFTF: Add ARMv8.5 BTI support in xlat_tables_v2 library TFTF: Add ARMv8.5 BTI support in assembler files TFTF: Add ARMv8.5 BTI-related definitions
2020-08-18TFTF: Add ARMv8.5 BTI support in assembler filesAlexei Fedorov
This patch adds BTI support in assembler files which fully correspond to those in TF-A source tree. Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Change-Id: Ie6a7b248c967684c6b2b86b915f0499fe095bba3
2020-07-20plat/arm: Move defines to platform specific header fileManish V Badarkhe
Some platform specific defines found in 'fwu_nvm.h' header hence moved such define to platform specific header file. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I1cfd1c95306e2ded5b78d1d6424ad159a958c502
2020-06-26Merge "Update FIP corrupt address"Sandrine Bailleux
2020-06-19SPM: TFTF test of FFA_VERSION interfaceJ-Alves
Implemented test to FFA_VERSION interface: - "test_ffa_version.c" contains functions to test FFA_VERSION ABI; - Test suite for FFA_VERSION ABI in tests-spm.xml; - Helper macros changed in "ffa_helpers.h". Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I6b0e937e30fceaa21a57c4ba0761a62049b16c0d
2020-06-09Update FIP corrupt addressManish V Badarkhe
Updated "FIP_CORRUPT_OFFSET" address which is used to corrupt BL2 in FIP. This address is being changed due to addition of fw-config image in FIP. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I003ccf9ba80b50646ed732b9306e5be757dbf4ff
2020-06-03Test that TF-A supports ARMv8.6-ECVJimmy Brisson
Note: This test will cause an unhandled exception in the case that TF-A is not doing its job and enabling ARMv8.6-ECV Self-Synch when the hardware supports it. Change-Id: Iee19963f31fa47b0010e77d7b56b05b71ec1b507 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-05-29Test that TF-A supports ARMv8.6-FGTJimmy Brisson
Note: This test will cause an unhandled exception in the case that TF-A is not doing its job and enabling ARMv8.6-FGT when the hardware supports it. Change-Id: Iae0fe39895909248b5e7b07a1a73f7702adce7dd Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-05-15SPCI is now called PSA FF-AJ-Alves
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA FF-A(in documents) or simply FFA(in code). Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I17728c1503312845944a5ba060c252c2b98f3e91
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