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This patch introduces initial support for Tegra186 platforms.
Verified with tftf-validation.
******************************* Summary *******************************
> Test suite 'Framework Validation'
Passed
> Test suite 'Timer framework Validation'
Passed
=================================
Tests Skipped : 0
Tests Passed : 6
Tests Failed : 0
Tests Crashed : 0
Total tests : 6
=================================
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I9c68fce2cbc14592dbb2738adbeb64ec33e910e8
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The function serror_sdei_event_handler has been defined in
inject_serror.S, Tegra194 has different function content
with the common function.
Rename it to tegra194_serror_sdei_event_handler.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I5a619abcf6aca5215da38f3a74fc229f5b2ec770
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The drivers: reset, timers. wake, watchdog can be used for
other nvidia platforms. Move them to drivers and remove the
t194 tag for the common functions and defines.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I658341ccd5d7a0fe21e65291c8ed71f9ccc93e5d
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* changes:
Tegra194: support GET_SMMU_PER testing
Tegra194: introduce tests to verify the Video Memory resize interface
Tegra194: skip sub-test to validate EL3 power state parsing
timers: remove dependency on SYS_CNT_BASE1
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This patch introduces a test to get return value from SMC SiP function
TEGRA_SIP_GET_SMMU_PER. This is a common function for all Tegra platforms.
This patch enables the test for Tegra194 platforms.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I14d82aecdbccc02ce3965b52230500bf487a0cc3
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Tegra platforms provide support to program the Video memory aperture and
increase or decrease the size at run time.
This test verifies the interface for the following positive and negative
scenarios:
* verify that incorrect input parameters are handled properly
* verify that the memory region is programmed and can be resized later
* verify that no information is leaked after the resize operation
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id554b2c565a85a62ba4524b2faf7d41d3d506f18
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Tegra194 platforms use all 28 bits of the PSTATE. This patch skips the
"Create all power states and validate EL3 power state parsing" from the
"EL3 power state parser validation" test suite as it is not in sync with
this expectation.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I7f5dc6ab17fe943e5dcf0e229f5c4b88a272cbb7
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The Arm ARM Section D11.1.1 titled "The full set of Generic Timer
components" says that Memory-mapped timers are optional. The timer
framework and tests use the SYS_CNT_BASE1 macro to read the memory
mapped timers. But they can also read the CNTPCT_EL0 system register
to get the same value to accommodate all Arm platforms.
This patch replaces the usage of SYS_CNT_BASE1 from the timer code
with calls to syscounter_read().
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I4d9ee5587351ee737800539f4d48606e7de80538
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SPs support receipt of direct message requests and is reported as
such in partition info get properties field.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I643f374cc9fa702fa839987ff576067589af867a
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* changes:
plat: tc0: Add cactus support
plat/arm: Add initial platform support for TC0
cactus: re-structure platform dependent files
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* changes:
Tegra194: disable boot requirement tests
Tegra194: skip PSCI STAT tests requiring PSTATE_TYPE_POWERDOWN
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Although there are not many variable default values and macros
definitions, for modularity and scalability, place these two into a
separate folder.
Change-Id: If916a69edda07aaeaa77d60ce482e002effd7f9f
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
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This includes one test with one seed as
the initial implementation. A future upgrade will include an enhanced
seeding strategy. The patch includes an example device tree file with
the actual test (sdei.dts) leveraging the SDEI functions that can be called
without reference to system state. Platform CI will have a single
TFTF config to be used in all future testing. Once both branches
of TFA tests and platform CI are checked in a user can invoke the
testing with:
workspace=<workspace location> test_groups=fvp-aarch64-sdei,fvp-smcfuzzing:fvp-tftf-fip.tftf-aemv8a test_run=1 bin_mode=debug retain_paths=1 ./platform-ci/script/run_local_ci.sh
Signed-off-by: Mark Dykes <mark.dykes@arm.com>
Change-Id: Ic290e7255bcfd845c0d22037e0b670a6691541df
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The package make is part of build-essential, which is previously
installed, thus there is no need to install it explicitly.
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: Ie95f2f87057ef144123578fd4e28668164eed3a3
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Tegra194 platforms do not support memory mapped timers. This patch
disables the "Boot requirement" test suite to disable the cntfrq
tests for the platform.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibf0092ec1a60520d1bdb7d0f4d39e5db7793644c
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Tegra194 platforms do not support CPU suspend with state type as
PSTATE_TYPE_POWERDOWN. As a result this patch disables the following
tests
* PSCI STAT/Stats test cases for CPU OFF
* PSCI STAT/Stats test cases after system suspend
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibc3f2be8ff0b00043aa657d4692b38e4ef04d5ad
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This patch adds tc0 platform support for cactus to execute at S-EL1
Change-Id: Iabac58de7c39e51968f0c5b578292e5a6111609a
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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This patch adds TC0 platform support for tf-a-tests.
Enables tftf and el3_payload build targets.
Change-Id: Ia93e867e27f96ba94b686fadde5a730ffa221cbc
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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This patch makes below changes to cactus:
- Platform dependent files are moved to spm/cactus/plat/arm/fvp
- Removes relative path dependency for cactus dts by copying it to build
directory.
- Platform dependent macros are defined in cactus_platform_def.h like
- Device base
- Console UART
- RX Base
- Execution context count
Change-Id: I59e3c3f8640e01e46fc91bee4d8ce4255eaf9737
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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Some generic parts of TFTF have dependencies from FVP platform
macros which can cause some trouble when porting the tests to a
different platform.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I11eb1af142b8c0ee1de2fcc8f298658bceedf306
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Previously, there were no tests using the RM_ANY routing mode. That
particular flag doesn't affect code flow very much, it's mainly used
for GIC configuration of the interrupt, so this is a test of basic
functionality.
This test case makes sure RM_ANY event registrtation works and that
events can be routed to all CPUs. It does this by registering an SDEI
event with the RM_ANY flag, powering up all CPUs, then generating
events. Each time a CPU receives an event it shuts off and the process
repeats. Every CPU must receive a single event or the test will not
pass.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1ebd0565158d93bddbf58d680d4696086ac00234
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According to "Combinations of cores" section in the
Arm DynamIQ Shared Unit Technical Reference Manual,
platforms with CPUs inside DynamIQ Shared Unit (DSU)
can have up to 8 CPUs in a cluster. One of the examples
of such platform is FVP_Base_Cortex-A55x4+Cortex-A76x2
which is used in CI tests. When running TFTF, test detects
only 4 Cortex-A55 CPUs and other 2 Cortex-A76 CPUs are
kept in power off state:
NOTICE: Cluster #0 [4 CPUs]
NOTICE: CPU #0 [MPID: 0x1000000]
NOTICE: CPU #1 [MPID: 0x1000100]
NOTICE: CPU #2 [MPID: 0x1000200]
NOTICE: CPU #3 [MPID: 0x1000300]
TFTF FVP topology for CPUs with single threads supports up to 4
clusters with up to 4 CPUs per cluster (default configuration
is 2 x 4) and thus cannot detect 2 extra CPUs in the same cluster.
This patch fixes this issue by setting maximum number of CPUs
in DSU cluster to 8.
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I18acd1728e566cabb2331c988a2da972f8be3aae
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If 'makefile' variables are expected to be overwritten by environment
and/or command line, it is better to use conditional assignment ('?=')
so it clearly indicates the variable intention and usage.
Change-Id: I890f71fe4bb26b5777b49e9904a1489ca8fad498
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
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* changes:
cactus: implement hvc call to get interrupt id
cactus: add exception/interrupt framework
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Since an SP cannot access GIC directly, it relies on SPMC(S-EL2) to
get the interrupt ID.
This patch introduces a new hvc call "SPM_INTERRUPT_GET" to get
interrupt ID in S-EL1.
Change-Id: I37626f907174ae57a24dc6b86e89d26ba8ebbddf
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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This patch adds following changes to cactus
1. Set up exception vector base address.
2. Add skeleton interrupt handler.
3. Install default tftf cpu exception handler.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I265553918b45a0e7e80ef0d7c48c09abfbec1a5f
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Hafnium provided VM get count and vcpu get count hypervisor calls which
are now deprecated [1]. The preference is to use FFA_PARTITION_INFO_GET
discovery ABI.
[1] https://git.trustedfirmware.org/hafnium/hafnium.git/
commit/?id=ae3840dbc9372fd407893f32a5d624828c8933ae
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idad95a0804a05d845dc45c2a0f0463f0120d4815
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* changes:
cactus: break the message loop on bad message request
cactus: re-align secure partition id
cactus: adjust the number of EC context to max number of PEs
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When the FF-A direct message request is not received as expected
prefer breaking the message loop and panicing rather than replying
with the FF-A error ABI to the SPMC. It is improper to use this
latter ABI in context of Hafnium as this is treated as an invalid
SMC issued by the SP.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I77cd0831a850e775f9996f4ecd1b5a81e6244a53
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According to [1] and [2] secure partition ids are defined from
0x8001 to 0xfffe. Update the cactus test payload and TFTF such
that it uses the appropriate IDs.
0x8000 and 0xffff are reserved FF-A IDs respectively for the SPMC
and the SPMD.
Conversely in the NWd, the Hypervisor ID is 0 and VMs are numbered
in the range of 1 to 0x7fff.
[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/
secure-partition-manager.html#ffa-id-get
[2] https://review.trustedfirmware.org/c/hafnium/hafnium/+/5165
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I3e9786212b227e6637a7650e60ddc4e59ad05a46
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According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
number of PEs (pinned MP). Adjust the cactus manifest execution-context
fields to maximum number of PEs.
[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/
secure-partition-manager.html#platform-topology
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I79aec4b685c8774acb9b52dd6b05674cebc6ad2e
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Instead of prefixing the 'do not echo command' '@', make help as
prerequisite of .SILENT. This avoids prefixing '@' in future help
messages.
Change-Id: If33b82b4d3bccc92e8de74703ff6af04387008a0
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>
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Program the memory mapped GIC_ITARGETSR register with appropriate
cpu mask and assert the expected value is returned upon reading
the register.
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I356111d763569c229d7f4c9ea3cd4899305a4954
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When the third cactus partition is booted, map the RXTX
region using the FFA_RXTX_MAP ABI. If this is successful,
point the mailbox to this RXTX region.
Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: Ifbe3bc70b187f75f29ef66356e714e8a905d2db8
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Add the third partition to the ffa_partition_info_get test to test
that a partition can successfully get information about the third cactus
partition
Signed-off-by: Ruari Phipps <ruari.phipps@arm.com>
Change-Id: Ib8c69f16e217f9631be005c7759753d05704afd2
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