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Diffstat (limited to 'plat/xilinx/versal/tests_to_skip.txt')
| -rw-r--r-- | plat/xilinx/versal/tests_to_skip.txt | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/plat/xilinx/versal/tests_to_skip.txt b/plat/xilinx/versal/tests_to_skip.txt new file mode 100644 index 0000000..8d8bc7c --- /dev/null +++ b/plat/xilinx/versal/tests_to_skip.txt @@ -0,0 +1,40 @@ +# +# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# +################################################################################ +# Disable the listed tests for Versal Platform. +################################################################################ + +#TESTS: tftf-validation +Framework Validation/Events API +Timer framework Validation/Target timer to a power down cpu +Timer framework Validation/Test scenario where multiple CPUs call same timeout + +#TESTS: psci +PSCI Affinity Info/Affinity info level0 powerdown +PSCI CPU Suspend/CPU suspend to powerdown at level 0 +PSCI CPU Suspend/CPU suspend to powerdown at level 1 +PSCI CPU Suspend/CPU suspend to powerdown at level 2 +PSCI CPU Suspend/CPU suspend to standby at level 0 +PSCI CPU Suspend/CPU suspend to standby at level 1 +PSCI CPU Suspend/CPU suspend to standby at level 2 +PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode +PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode +CPU Hotplug/Invalid entry point +PSCI System Suspend Validation/System suspend multiple times +PSCI System Suspend Validation/system suspend from all cores +PSCI System Suspend Validation/Validate suspend to RAM functionality + +#TESTS: el3-power-state +EL3 power state parser validation/Create all power states and validate EL3 power state parsing +EL3 power state parser validation/Create invalid local power state at all levels and validate EL3 power state parsing +EL3 power state parser validation/Create invalid power state type and validate EL3 power state parsing +EL3 power state parser validation/Create a power state with valid and invalid local state ID at different levels and validate power state parsing + +#TESTS: psci-extensive +PSCI CPU ON OFF Stress Tests/PSCI CPU ON OFF stress test +PSCI CPU ON OFF Stress Tests/Repeated hotplug of all cores to stress test CPU_ON and CPU_OFF +PSCI CPU ON OFF Stress Tests/Random hotplug cores in a large iteration to stress boot path code |