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| author | Manish Pandey <manish.pandey2@arm.com> | 2020-06-09 14:39:45 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-06-09 14:39:45 +0000 |
| commit | 87c9a5cc97c16f6c1c991fab334bfed4e4fce296 (patch) | |
| tree | bf3c91e4eebda0e129be310642d0ebdaad9302ee /tftf | |
| parent | 5861730b3d6333f936c2fcecaa034de0391cbd94 (diff) | |
| parent | 00ed5a4b3b0ddfeb925708e3afb037cc89ebd816 (diff) | |
Merge changes from topic "tegra194-platform-support"
* changes:
tests: arm_arch_svc: introduce support for NVIDIA Denver CPUs
Tegra194: introduce per-CPU Hypervisor Timer Interrupt ID
Tegra194: skip some timer framework validation tests
Tegra194: introduce watchdog timer
Tegra194: timers: increase the step value to 5ms
Tegra194: create dummy SMMU context for system resume
Tegra194: introduce system reset
Tegra194: disable some system suspend test cases
Tegra194: skip CPU suspend tests requiring SGI as wake source
Tegra194: wake: introduce support for RTC as wake source
Tegra194: pwr_mgmt: introduce power management support
plat: nvidia: introduce platform port for Tegra194
drivers: ti: uart: introduce UART 16550 driver
Diffstat (limited to 'tftf')
| -rw-r--r-- | tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c index e88f183..93abf15 100644 --- a/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c +++ b/tftf/tests/runtime_services/arm_arch_svc/smccc_arch_workaround_1.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2018-2020, Arm Limited. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,9 +20,15 @@ #define CORTEX_A72_MIDR 0x410FD080 #define CORTEX_A73_MIDR 0x410FD090 #define CORTEX_A75_MIDR 0x410FD0A0 +#define DENVER_MIDR_PN0 0x4E0F0000 +#define DENVER_MIDR_PN1 0x4E0F0010 +#define DENVER_MIDR_PN2 0x4E0F0020 +#define DENVER_MIDR_PN3 0x4E0F0030 +#define DENVER_MIDR_PN4 0x4E0F0040 static int cortex_a57_test(void); static int csv2_test(void); +static int denver_test(void); static struct ent { unsigned int midr; @@ -31,6 +38,11 @@ static struct ent { { .midr = CORTEX_A72_MIDR, .wa_required = csv2_test }, { .midr = CORTEX_A73_MIDR, .wa_required = csv2_test }, { .midr = CORTEX_A75_MIDR, .wa_required = csv2_test }, + { .midr = DENVER_MIDR_PN0, .wa_required = denver_test }, + { .midr = DENVER_MIDR_PN1, .wa_required = denver_test }, + { .midr = DENVER_MIDR_PN2, .wa_required = denver_test }, + { .midr = DENVER_MIDR_PN3, .wa_required = denver_test }, + { .midr = DENVER_MIDR_PN4, .wa_required = denver_test }, }; static int cortex_a57_test(void) @@ -48,6 +60,11 @@ static int csv2_test(void) return 1; } +static int denver_test(void) +{ + return 1; +} + static test_result_t test_smccc_entrypoint(void) { smc_args args; |