Tegra186: introduce platform support

This patch introduces initial support for Tegra186 platforms.

Verified with tftf-validation.

******************************* Summary *******************************
> Test suite 'Framework Validation'
                                                                Passed
> Test suite 'Timer framework Validation'
                                                                Passed
=================================
Tests Skipped : 0
Tests Passed  : 6
Tests Failed  : 0
Tests Crashed : 0
Total tests   : 6
=================================

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I9c68fce2cbc14592dbb2738adbeb64ec33e910e8

9 files changed, 567 insertions, 0 deletions

diff --git a/plat/nvidia/tegra186/helpers.S b/plat/nvidia/tegra186/helpers.S
new file mode 100644
index 0000000..7ffbe3e
--- /dev/null
+++ b/plat/nvidia/tegra186/helpers.S
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+	.globl	platform_get_core_pos
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
+
+	/*
+	 * Return 0 to 7 as logical CPU IDs
+	 */
+func platform_get_core_pos
+	lsr	x1, x0, #MPIDR_AFF0_SHIFT
+	and	x1, x1, #MPIDR_AFFLVL_MASK /* core id */
+	lsr	x2, x0, #MPIDR_AFF1_SHIFT
+	and	x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */
+
+	/* core_id > PLATFORM_CORES_CLUSTER1 */
+	mov	x0, #-1
+	cmp	x1, #(PLATFORM_CORES_CLUSTER1 - 1)
+	b.hi	1f
+
+	/* cluster_id > PLATFORM_CLUSTER_COUNT */
+	cmp	x2, #(PLATFORM_CLUSTER_COUNT - 1)
+	b.hi	1f
+
+	/* CorePos = CoreId + (ClusterId * cpus per cluster) */
+	mov	x3, #PLATFORM_CORES_CLUSTER1
+	mul	x3, x2, x3
+	add	x0, x1, x3
+
+1:
+	ret
+endfunc platform_get_core_pos
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_init(void)
+	 * Function to initialize the crash console
+	 * without a C Runtime to print crash report.
+	 * Clobber list : x0 - x4
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_init
+	mov_imm	x0, TEGRA_UARTA_BASE
+	mov_imm	x1, TEGRA_CONSOLE_CLKRATE
+	mov_imm	x2, TEGRA_CONSOLE_BAUDRATE
+	b	console_init
+endfunc plat_crash_console_init
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_putc(int c)
+	 * Function to print a character on the crash
+	 * console without a C Runtime.
+	 * Clobber list : x1, x2
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_putc
+	mov_imm	x1, TEGRA_UARTA_BASE
+	b	console_putc
+endfunc plat_crash_console_putc
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_flush()
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0 - x1
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_flush
+	mov_imm	x1, TEGRA_UARTA_BASE
+	b	console_flush
+endfunc plat_crash_console_flush
diff --git a/plat/nvidia/tegra186/include/platform_def.h b/plat/nvidia/tegra186/include/platform_def.h
new file mode 100644
index 0000000..d746aee
--- /dev/null
+++ b/plat/nvidia/tegra186/include/platform_def.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <utils_def.h>
+
+/*******************************************************************************
+ * Platform definitions used by common code
+ ******************************************************************************/
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Tegra DRAM memory base address
+ ******************************************************************************/
+#define DRAM_BASE			U(0x80000000)
+#define DRAM_END			U(0xB0000000)
+#define DRAM_SIZE			(DRAM_END - DRAM_BASE)
+
+/*******************************************************************************
+ * Run-time address of the TFTF image.
+ * It has to match the location where the Trusted Firmware-A loads the BL33
+ * image.
+ ******************************************************************************/
+#define TFTF_BASE			0x80600000
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Translation table constants */
+#define MAX_XLAT_TABLES			20
+#define MAX_MMAP_REGIONS		20
+
+/* stack memory available to each CPU */
+#define PLATFORM_STACK_SIZE		0x1400
+#define PCPU_DV_MEM_STACK_SIZE		0x100
+
+/* total number of system nodes implemented by the platform */
+#define PLATFORM_SYSTEM_COUNT		1
+
+/* total number of clusters implemented by the platform */
+#define PLATFORM_CLUSTER_COUNT		2
+#define PLATFORM_CORES_CLUSTER0		2
+#define PLATFORM_CORES_CLUSTER1		4
+
+/* total number of CPUs implemented by the platform across all clusters */
+#define PLATFORM_CORE_COUNT		(PLATFORM_CORES_CLUSTER0 + \
+					 PLATFORM_CORES_CLUSTER1)
+
+/* total number of nodes in the affinity hierarchy at all affinity levels */
+#define PLATFORM_NUM_AFFS		(PLATFORM_SYSTEM_COUNT + \
+					 PLATFORM_CLUSTER_COUNT + \
+					 PLATFORM_CORE_COUNT)
+
+/*
+ * maximum number of affinity levels in the system that the platform
+ * implements
+ */
+#define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LEVEL		PLATFORM_MAX_AFFLVL
+
+/*
+ * Defines the maximum number of power states at a power domain level for the
+ * platform.
+ */
+#define PLAT_MAX_PWR_STATES_PER_LVL	2
+
+/*
+ * Defines the offset of the last Shared Peripheral Interrupt supported by the
+ * TF-A Tests on this platform. SPI numbers are mapped onto GIC interrupt IDs,
+ * starting from interrupt ID 32. This offset ID corresponds to the last SPI
+ * number, to which 32 must be added to get the corresponding last GIC IRQ ID.
+ */
+#define PLAT_MAX_SPI_OFFSET_ID		280
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH		4
+
+/*
+ * We want to run without support for non-volatile memory and hence using a
+ * portion of DRAM as workaround.
+ */
+#define TFTF_NVM_OFFSET			0x0FA00000
+#define TFTF_NVM_SIZE			0x10000000
+
+/*
+ * Times (in ms) used by test code for completion of different events.
+ * Suspend entry time for debug build is high due to the time taken
+ * by the VERBOSE/INFO prints. The value considers the worst case scenario
+ * where all CPUs are going and coming out of suspend continuously.
+ */
+#define PLAT_SUSPEND_ENTRY_TIME		500
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME	1000
+
+/*******************************************************************************
+ * Non-Secure Software Generated Interupts IDs
+ ******************************************************************************/
+#define IRQ_NS_SGI_0			0
+#define IRQ_NS_SGI_1			1
+#define IRQ_NS_SGI_2			2
+#define IRQ_NS_SGI_3			3
+#define IRQ_NS_SGI_4			4
+#define IRQ_NS_SGI_5			5
+#define IRQ_NS_SGI_6			6
+#define IRQ_NS_SGI_7			7
+
+/*******************************************************************************
+ * Per-CPU Hypervisor Timer Interrupt ID
+ ******************************************************************************/
+#define IRQ_PCPU_HP_TIMER		26
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 40)
+
+/*******************************************************************************
+ * Used to align variables on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT		6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+/*******************************************************************************
+ * Platform console related constants
+ ******************************************************************************/
+#define TEGRA_CONSOLE_BAUDRATE		U(115200)
+#define TEGRA_CONSOLE_CLKRATE		U(408000000)
+
+/*******************************************************************************
+ * Platform MMIO devices
+ ******************************************************************************/
+#define TEGRA_MC_BASE			U(0x02C10000)
+#define TEGRA_TMR0_BASE			U(0x03020000)
+#define TEGRA_WDT0_BASE			U(0x030c0000)
+#define TEGRA_UARTA_BASE		U(0x03100000)
+#define TEGRA_GICD_BASE			U(0x03881000)
+#define TEGRA_GICC_BASE			U(0x03882000)
+#define TEGRA_RTC_BASE			U(0x0C2A0000)
+#define TEGRA_TMRUS_BASE		U(0x0C2E0000)
+#define SYS_CNT_BASE1			TEGRA_TMRUS_BASE
+#define TEGRA_AOWAKE_BASE		U(0x0C370000)
+#define TEGRA_SCRATCH_BASE		U(0x0C390000)
+#define TEGRA_SMMU0_BASE		U(0x12000000)
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Platform functions
+ */
+void tegra_pwr_mgmt_setup(void);
+void tegra_set_rtc_as_wakeup_source(void);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/nvidia/tegra186/platform.mk b/plat/nvidia/tegra186/platform.mk
new file mode 100644
index 0000000..b7042e6
--- /dev/null
+++ b/plat/nvidia/tegra186/platform.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_INCLUDES		:=	-Iplat/nvidia/tegra186/include/
+
+PLAT_SOURCES		:=	drivers/arm/gic/arm_gic_v2.c			\
+				drivers/arm/gic/gic_common.c			\
+				drivers/arm/gic/gic_v2.c			\
+				drivers/arm/timer/private_timer.c		\
+				drivers/ti/uart/aarch64/16550_console.S		\
+				plat/nvidia/drivers/reset/reset.c		\
+				plat/nvidia/drivers/timer/timers.c		\
+				plat/nvidia/drivers/wake/wake.c			\
+				plat/nvidia/tegra186/helpers.S			\
+				plat/nvidia/tegra186/pwr_state.c		\
+				plat/nvidia/tegra186/setup.c			\
+				plat/nvidia/tegra186/topology.c			\
+				plat/nvidia/tegra186/watchdog.c
+
+PLAT_TESTS_SKIP_LIST	:=	plat/nvidia/tegra186/tests_to_skip.txt
+
+TFTF_CFLAGS		+=	-Wno-maybe-uninitialized
+
+ENABLE_ASSERTIONS	:=	1
+
+PLAT_SUPPORTS_NS_RESET	:=	1
+
+# Process PLAT_SUPPORTS_NS_RESET flag
+$(eval $(call assert_boolean,PLAT_SUPPORTS_NS_RESET))
+$(eval $(call add_define,TFTF_DEFINES,PLAT_SUPPORTS_NS_RESET))
+
+ifeq ($(USE_NVM),1)
+$(error "Tegra186 port of TFTF doesn't currently support USE_NVM=1")
+endif
diff --git a/plat/nvidia/tegra186/pwr_state.c b/plat/nvidia/tegra186/pwr_state.c
new file mode 100644
index 0000000..5c2753b
--- /dev/null
+++ b/plat/nvidia/tegra186/pwr_state.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <platform.h>
+#include <stddef.h>
+
+#include <psci.h>
+#include <utils_def.h>
+
+/*
+ * State IDs for local power states
+ */
+#define TEGRA186_RUN_STATE_ID		U(0) /* Valid for CPUs and Clusters */
+#define TEGRA186_CORE_RETN_STATE_ID	U(6) /* Valid for only CPUs */
+#define TEGRA186_CORE_OFF_STATE_ID	U(7) /* Valid for CPUs and Clusters */
+#define TEGRA186_SOC_OFF_STATE_ID	U(2) /* Valid for the System */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+	TEGRA186_RUN_DEPTH = 0,
+	TEGRA186_CORE_RETENTION_DEPTH,
+	TEGRA186_CORE_OFF_DEPTH,
+	TEGRA186_SYSTEM_OFF_DEPTH
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+	{TEGRA186_CORE_OFF_DEPTH, TEGRA186_CORE_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0}
+};
+
+/*
+ * The state property array with details of idle state possible
+ * for the cluster
+ */
+static const plat_state_prop_t cluster_state_prop[] = {
+	{TEGRA186_CORE_OFF_DEPTH, TEGRA186_CORE_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0}
+};
+
+/*
+ * The state property array with details of idle state possible
+ * for the system. Currently Tegra186 does not support CPU SUSPEND
+ * at system power level.
+ */
+static const plat_state_prop_t system_state_prop[] = {
+	{TEGRA186_SYSTEM_OFF_DEPTH, TEGRA186_SOC_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0}
+};
+
+/*
+ * This functions returns the plat_state_prop_t array for all the valid low
+ * power states from platform for a specified affinity level and returns NULL
+ * for an invalid affinity level. The array is expected to be NULL-terminated.
+ * This function is expected to be used by tests that need to compose the power
+ * state parameter for use in PSCI_CPU_SUSPEND API or PSCI_STAT/RESIDENCY
+ * API.
+ */
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+	switch (level) {
+	case MPIDR_AFFLVL0:
+		return core_state_prop;
+	case MPIDR_AFFLVL1:
+		return cluster_state_prop;
+	case MPIDR_AFFLVL2:
+		return system_state_prop;
+	default:
+		return NULL;
+	}
+}
diff --git a/plat/nvidia/tegra186/setup.c b/plat/nvidia/tegra186/setup.c
new file mode 100644
index 0000000..5e27543
--- /dev/null
+++ b/plat/nvidia/tegra186/setup.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <drivers/console.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gic_v2.h>
+#include <platform.h>
+#include <platform_def.h>
+
+#include <xlat_tables_v2.h>
+
+/*
+ * Memory map
+ */
+static const mmap_region_t tegra186_mmap[] = {
+	MAP_REGION_FLAT(TEGRA_MC_BASE, 0x2000, /* 8KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_TMR0_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_WDT0_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x10000U, /* 64KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_RTC_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_AOWAKE_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000, /* 4KB */
+			MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE,
+			MT_MEMORY | MT_RW | MT_NS),
+	{0}
+};
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+	return tegra186_mmap;
+}
+
+void tftf_plat_arch_setup(void)
+{
+	tftf_plat_configure_mmu();
+}
+
+void tftf_early_platform_setup(void)
+{
+	/* Tegra186 platforms use UARTA as the console */
+	console_init(TEGRA_UARTA_BASE, TEGRA_CONSOLE_CLKRATE,
+			TEGRA_CONSOLE_BAUDRATE);
+}
+
+void tftf_platform_setup(void)
+{
+	gicv2_init(TEGRA_GICC_BASE, TEGRA_GICD_BASE);
+	gicv2_setup_distif();
+	gicv2_probe_gic_cpu_id();
+	gicv2_setup_cpuif();
+
+	/* Configure system suspend wake sources */
+	tegra_set_rtc_as_wakeup_source();
+}
diff --git a/plat/nvidia/tegra186/tests.xml b/plat/nvidia/tegra186/tests.xml
new file mode 100644
index 0000000..03153f3
--- /dev/null
+++ b/plat/nvidia/tegra186/tests.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+  Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-3-Clause
+-->
+
+
+<!-- External references to all individual tests files. -->
+<!DOCTYPE testsuites [
+  <!ENTITY tests-tftf-validation SYSTEM "../../../tftf/tests/tests-tftf-validation.xml">
+]>
+
+<testsuites>
+
+  &tests-tftf-validation;
+
+</testsuites>
diff --git a/plat/nvidia/tegra186/tests_to_skip.txt b/plat/nvidia/tegra186/tests_to_skip.txt
new file mode 100644
index 0000000..1a18495
--- /dev/null
+++ b/plat/nvidia/tegra186/tests_to_skip.txt
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020, NVIDIA Coprporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+################################################################################
+# Disable the following tests from tests-psci.xml as a result
+################################################################################
+
+# Tegra186 platforms cannot be woken up from CPU_SUSPEND by an SGI
+PSCI Affinity Info/Affinity info level0 powerdown
+PSCI CPU Suspend/CPU suspend to standby at level 0
+PSCI CPU Suspend/CPU suspend to standby at level 1
+PSCI CPU Suspend/CPU suspend to standby at level 2
+PSCI System Suspend Validation/Suspend system with cores in suspend
+
+# Tegra186 platforms are facing problems with system suspend
+PSCI System Suspend Validation
+
+# Tegra186 platforms do not support CPU suspend with PSTATE_TYPE_POWERDOWN
+PSCI STAT/Stats test cases for CPU OFF
+PSCI STAT/Stats test cases after system suspend
+
+# Tegra186 platforms do not support memory mapped timers
+Boot requirement tests
+
+# CPUs cannot be woken up with a timer interrupt after power off
+Timer framework Validation/Target timer to a power down cpu
+Timer framework Validation/Test scenario where multiple CPUs call same timeout
+Timer framework Validation/Stress test the timer framework
+
+# Tegra186 uses all 27:0 bits of the PSTATE
+EL3 power state parser validation/Create all power states and validate EL3 power state parsing
+EL3 power state parser validation/Create a power state with valid and invalid local state ID at different levels and validate power state parsing
diff --git a/plat/nvidia/tegra186/topology.c b/plat/nvidia/tegra186/topology.c
new file mode 100644
index 0000000..02fadb3
--- /dev/null
+++ b/plat/nvidia/tegra186/topology.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <assert.h>
+#include <plat_topology.h>
+#include <stddef.h>
+
+#include <tftf_lib.h>
+#include <platform_def.h>
+
+static const struct {
+	unsigned cluster_id;
+	unsigned cpu_id;
+} tegra186_cores[] = {
+	{ 0, 0 },
+	{ 0, 1 },
+	{ 1, 0 },
+	{ 1, 1 },
+	{ 1, 2 },
+	{ 1, 3 }
+};
+
+/*
+ * The Tegra186 power domain tree descriptor. Tegra186 implements a system
+ * power domain at the level 2. The first entry in the power domain descriptor
+ * specifies the number of power domains at the highest power level.
+ */
+static const unsigned char tegra186_power_domain_tree_desc[] = {
+	/* Number of root nodes */
+	PLATFORM_SYSTEM_COUNT,
+	/* Number of children of root node */
+	PLATFORM_CLUSTER_COUNT,
+	/* Number of children for the first cluster */
+	PLATFORM_CORES_CLUSTER0,
+	/* Number of children for the second cluster */
+	PLATFORM_CORES_CLUSTER1
+};
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+	return tegra186_power_domain_tree_desc;
+}
+
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+	assert(core_pos < PLATFORM_CORE_COUNT);
+
+	return (uint64_t)make_mpid(tegra186_cores[core_pos].cluster_id,
+				tegra186_cores[core_pos].cpu_id);
+}
diff --git a/plat/nvidia/tegra186/watchdog.c b/plat/nvidia/tegra186/watchdog.c
new file mode 100644
index 0000000..08d1fa4
--- /dev/null
+++ b/plat/nvidia/tegra186/watchdog.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+
+/*
+ * Start the watchdog timer
+ */
+void tftf_platform_watchdog_set(void)
+{
+	; /* do nothing */
+}
+
+/*
+ * Stop the watchdog timer
+ */
+void tftf_platform_watchdog_reset(void)
+{
+	; /* do nothing */
+}