plat/arm: Remove board/ directory

The board/ directory does not actually bring any benefit. There's no
need to separate the board level from any other level. Thus, this
patch flattens the Arm platform tree like so:

plat/arm/
|- common
|- fvp
|- juno
|- sgi
|   |- common
|   |- sgi575

Change-Id: I10e4af7594bb555d912222a881d95eae9864637e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

9 files changed, 727 insertions, 0 deletions

diff --git a/plat/arm/fvp/aarch32/plat_helpers.S b/plat/arm/fvp/aarch32/plat_helpers.S
new file mode 100644
index 0000000..1d923ad
--- /dev/null
+++ b/plat/arm/fvp/aarch32/plat_helpers.S
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <pl011.h>
+#include "../fvp_def.h"
+
+	.globl	platform_get_core_pos
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(unsigned long mpid)
+ *
+ * Function to calculate the core position on FVP.
+ *
+ * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) +
+ * (CPUId * FVP_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func platform_get_core_pos
+	/*
+	 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
+	 * look as if in a multi-threaded implementation
+	 */
+	tst	r0, #MPIDR_MT_MASK
+	mov	r3, r0
+	lsleq	r3, r0, #MPIDR_AFFINITY_BITS
+
+	/* Extract individual affinity fields from MPIDR */
+	ubfx	r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+	/* Compute linear position */
+	mov	r3, #FVP_MAX_CPUS_PER_CLUSTER
+	mla	r1, r2, r3, r1
+	mov	r3, #FVP_MAX_PE_PER_CPU
+	mla	r0, r1, r3, r0
+
+	bx	lr
+endfunc platform_get_core_pos
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_init(void)
+	 * Function to initialize the crash console
+	 * without a C Runtime to print crash report.
+	 * Clobber list : x0 - x4
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_init
+	ldr	r0, =PLAT_ARM_UART_BASE
+	ldr	r1, =PLAT_ARM_UART_CLK_IN_HZ
+	ldr	r2, =PL011_BAUDRATE
+	b	console_core_init
+endfunc plat_crash_console_init
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_putc(int c)
+	 * Function to print a character on the crash
+	 * console without a C Runtime.
+	 * Clobber list : x1, x2
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_putc
+	ldr	r1, =PLAT_ARM_UART_BASE
+	b	console_core_putc
+endfunc plat_crash_console_putc
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_flush()
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0 - r1
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_flush
+	ldr	r1, =PLAT_ARM_UART_BASE
+	b	console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/arm/fvp/aarch64/plat_helpers.S b/plat/arm/fvp/aarch64/plat_helpers.S
new file mode 100644
index 0000000..4bd9f3d
--- /dev/null
+++ b/plat/arm/fvp/aarch64/plat_helpers.S
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <pl011.h>
+#include "../fvp_def.h"
+
+	.globl	platform_get_core_pos
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_crash_console_flush
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(unsigned long mpid)
+ *
+ * Function to calculate the core position on FVP.
+ *
+ * (ClusterId * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) +
+ * (CPUId * FVP_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * FVP_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func platform_get_core_pos
+	/*
+	 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
+	 * look as if in a multi-threaded implementation.
+	 */
+	tst	x0, #MPIDR_MT_MASK
+	lsl	x3, x0, #MPIDR_AFFINITY_BITS
+	csel	x3, x3, x0, eq
+
+	/* Extract individual affinity fields from MPIDR */
+	ubfx	x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+	ubfx	x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+	/* Compute linear position */
+	mov	x3, #FVP_MAX_CPUS_PER_CLUSTER
+	madd	x1, x2, x3, x1
+	mov	x3, #FVP_MAX_PE_PER_CPU
+	madd	x0, x1, x3, x0
+	ret
+endfunc platform_get_core_pos
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_init(void)
+	 * Function to initialize the crash console
+	 * without a C Runtime to print crash report.
+	 * Clobber list : x0 - x4
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_init
+	mov_imm	x0, PLAT_ARM_UART_BASE
+	mov_imm	x1, PLAT_ARM_UART_CLK_IN_HZ
+	mov_imm	x2, PL011_BAUDRATE
+	b	console_core_init
+endfunc plat_crash_console_init
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_putc(int c)
+	 * Function to print a character on the crash
+	 * console without a C Runtime.
+	 * Clobber list : x1, x2
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_putc
+	mov_imm	x1, PLAT_ARM_UART_BASE
+	b	console_core_putc
+endfunc plat_crash_console_putc
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_flush()
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0 - r1
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_flush
+	mov_imm	x1, PLAT_ARM_UART_BASE
+	b	console_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/arm/fvp/fvp_def.h b/plat/arm/fvp/fvp_def.h
new file mode 100644
index 0000000..46323e4
--- /dev/null
+++ b/plat/arm/fvp/fvp_def.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*******************************************************************************
+ * FVP specific definitions. Used only by FVP specific code.
+ ******************************************************************************/
+
+#ifndef __FVP_DEF_H__
+#define __FVP_DEF_H__
+
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Cluster Topology definitions
+ ******************************************************************************/
+#define FVP_MAX_CPUS_PER_CLUSTER	4
+/* Currently the highest cluster count on the FVP is 4 (Quad cluster) */
+#define FVP_CLUSTER_COUNT		4
+/* Currently multi-threaded CPUs only have a single thread */
+#define FVP_MAX_PE_PER_CPU		1
+
+/*******************************************************************************
+ * FVP memory map related constants
+ ******************************************************************************/
+
+#define DEVICE0_BASE		0x1a000000
+#define DEVICE0_SIZE		0x12200000
+
+#define DEVICE1_BASE		0x2f000000
+#define DEVICE1_SIZE		0x400000
+
+/*******************************************************************************
+ * GIC-400 & interrupt handling related constants
+ ******************************************************************************/
+/* Base FVP compatible GIC memory map */
+#define GICD_BASE		0x2f000000
+#define GICR_BASE		0x2f100000
+#define GICC_BASE		0x2c000000
+
+/*******************************************************************************
+ * PL011 related constants
+ ******************************************************************************/
+#define PL011_UART0_BASE	0x1c090000
+#define PL011_UART1_BASE	0x1c0a0000
+#define PL011_UART2_BASE	0x1c0b0000
+#define PL011_UART3_BASE	0x1c0c0000
+
+#define PL011_UART0_CLK_IN_HZ	24000000
+#define PL011_UART1_CLK_IN_HZ	24000000
+#define PL011_UART2_CLK_IN_HZ	24000000
+#define PL011_UART3_CLK_IN_HZ	24000000
+
+#define PLAT_ARM_UART_BASE		PL011_UART0_BASE
+#define PLAT_ARM_UART_CLK_IN_HZ		PL011_UART0_CLK_IN_HZ
+
+#endif /* __FVP_DEF_H__ */
diff --git a/plat/arm/fvp/fvp_mem_prot.c b/plat/arm/fvp/fvp_mem_prot.c
new file mode 100644
index 0000000..6a7d651
--- /dev/null
+++ b/plat/arm/fvp/fvp_mem_prot.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+#include <psci.h>
+#include <utils_def.h>
+#include <xlat_tables_v2.h>
+
+#define NS_IMAGE_OFFSET      TFTF_BASE
+#define NS_IMAGE_LIMIT       (NS_IMAGE_OFFSET + (32 << TWO_MB_SHIFT))
+
+static const mem_region_t fvp_ram_ranges[] = {
+	{NS_IMAGE_LIMIT, 1 << ONE_GB_SHIFT},
+#ifdef AARCH64
+	{FVP_DRAM2_BASE, 1 << ONE_GB_SHIFT},
+#endif
+};
+
+const mem_region_t *plat_get_prot_regions(int *nelem)
+{
+	*nelem = ARRAY_SIZE(fvp_ram_ranges);
+	return fvp_ram_ranges;
+}
diff --git a/plat/arm/fvp/fvp_pwr_state.c b/plat/arm/fvp/fvp_pwr_state.c
new file mode 100644
index 0000000..394818b
--- /dev/null
+++ b/plat/arm/fvp/fvp_pwr_state.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <platform.h>
+#include <psci.h>
+#include <stddef.h>
+
+/*
+ * State IDs for local power states on the FVP.
+ */
+#define FVP_RUN_STATE_ID	0	/* Valid for CPUs and Clusters */
+#define FVP_RETENTION_STATE_ID	1	/* Valid for only CPUs */
+#define FVP_OFF_STATE_ID	2	/* Valid for CPUs and Clusters */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+	FVP_RUN_DEPTH = 0,
+	FVP_RETENTION_DEPTH,
+	FVP_OFF_DEPTH,
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+	{FVP_RETENTION_DEPTH, FVP_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+	{FVP_OFF_DEPTH, FVP_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+/* The state property array with details of idle state possible
+   for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+	{FVP_OFF_DEPTH, FVP_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+/* The state property array with details of idle state possible
+   for the system level */
+static const plat_state_prop_t system_state_prop[] = {
+	{FVP_OFF_DEPTH, FVP_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+	{0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+	switch (level) {
+	case MPIDR_AFFLVL0:
+		return core_state_prop;
+	case MPIDR_AFFLVL1:
+		return cluster_state_prop;
+	case MPIDR_AFFLVL2:
+		return system_state_prop;
+	default:
+		return NULL;
+	}
+}
diff --git a/plat/arm/fvp/fvp_topology.c b/plat/arm/fvp/fvp_topology.c
new file mode 100644
index 0000000..348f8ef
--- /dev/null
+++ b/plat/arm/fvp/fvp_topology.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <assert.h>
+#include <mmio.h>
+#include <plat_topology.h>
+#include <platform_def.h>
+#include <stddef.h>
+#include <tftf_lib.h>
+
+/* FVP Power controller based defines */
+#define PWRC_BASE		0x1c100000
+#define PSYSR_OFF		0x10
+#define PSYSR_INVALID		0xffffffff
+
+static const struct {
+	unsigned int cluster_id;
+	unsigned int cpu_id;
+} fvp_base_aemv8a_aemv8a_cores[] = {
+	/* Cluster 0 */
+	{ 0, 0 },
+	{ 0, 1 },
+	{ 0, 2 },
+	{ 0, 3 },
+	/* Cluster 1 */
+	{ 1, 0 },
+	{ 1, 1 },
+	{ 1, 2 },
+	{ 1, 3 },
+	/* Cluster 2 */
+	{ 2, 0 },
+	{ 2, 1 },
+	{ 2, 2 },
+	{ 2, 3 },
+	/* Cluster 3 */
+	{ 3, 0 },
+	{ 3, 1 },
+	{ 3, 2 },
+	{ 3, 3 },
+};
+
+/*
+ * The FVP power domain tree descriptor. We always construct a topology
+ * with the maximum number of cluster nodes possible for FVP. During
+ * TFTF initialization, the actual number of nodes present on the model
+ * will be queried dynamically using `tftf_plat_get_mpidr()`.
+ * The FVP power domain tree does not have a single system level power domain
+ * i.e. a single root node. The first entry in the power domain descriptor
+ * specifies the number of power domains at the highest power level which
+ * is equal to FVP_CLUSTER_COUNT.
+ */
+static const unsigned char fvp_power_domain_tree_desc[] = {
+	/* Number of system nodes */
+	1,
+	/* Number of cluster nodes */
+	FVP_CLUSTER_COUNT,
+	/* Number of children for the first node */
+	FVP_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the second node */
+	FVP_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the third node */
+	FVP_MAX_CPUS_PER_CLUSTER,
+	/* Number of children for the fourth node */
+	FVP_MAX_CPUS_PER_CLUSTER
+};
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+	return fvp_power_domain_tree_desc;
+}
+
+static unsigned int fvp_pwrc_read_psysr(unsigned long mpidr)
+{
+	unsigned int rc;
+	mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
+	rc = mmio_read_32(PWRC_BASE + PSYSR_OFF);
+	return rc;
+}
+
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+	unsigned int mpid;
+
+	assert(core_pos < PLATFORM_CORE_COUNT);
+
+	mpid = make_mpid(
+			fvp_base_aemv8a_aemv8a_cores[core_pos].cluster_id,
+			fvp_base_aemv8a_aemv8a_cores[core_pos].cpu_id);
+
+	if (fvp_pwrc_read_psysr(mpid) != PSYSR_INVALID)
+		return mpid;
+
+	return INVALID_MPID;
+}
diff --git a/plat/arm/fvp/include/platform_def.h b/plat/arm/fvp/include/platform_def.h
new file mode 100644
index 0000000..55477b4
--- /dev/null
+++ b/plat/arm/fvp/include/platform_def.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include "../fvp_def.h"
+
+/*******************************************************************************
+ * Platform definitions used by common code
+ ******************************************************************************/
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#ifndef AARCH32
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+#else
+#define PLATFORM_LINKER_FORMAT		"elf32-littlearm"
+#define PLATFORM_LINKER_ARCH		arm
+#endif
+
+/*******************************************************************************
+ * Run-time address of the TFTF image.
+ * It has to match the location where the Trusted Firmware-A loads the BL33
+ * image.
+ ******************************************************************************/
+#define TFTF_BASE			0x88000000
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE			0x1C0F0000
+
+/*******************************************************************************
+ * Base address and size of external NVM flash
+ ******************************************************************************/
+#define FLASH_BASE			0x08000000
+
+/*
+ * The flash memory in FVP resembles as a SCSP package of 2-die's and
+ * of a total size of 512Mb, we are using only the main blocks of size
+ * 128KB for storing results. Also the FVP performs data striping and
+ * splits the word into half to each flash die's which leads to a
+ * virtual block size of 256KB to software.
+ */
+#define NOR_FLASH_BLOCK_SIZE		0x40000 /* 256KB */
+#define NOR_FLASH_BLOCKS_COUNT		255
+#define FLASH_SIZE			(NOR_FLASH_BLOCK_SIZE * NOR_FLASH_BLOCKS_COUNT)
+
+/*******************************************************************************
+ * Base address and size for the FIP that contains FWU images.
+ ******************************************************************************/
+#define PLAT_ARM_FWU_FIP_BASE		(FLASH_BASE + 0x400000)
+#define PLAT_ARM_FWU_FIP_SIZE		(0x100000)
+
+/*******************************************************************************
+ * Base address and size for non-trusted SRAM.
+ ******************************************************************************/
+#define NSRAM_BASE				(0x2e000000)
+#define NSRAM_SIZE				(0x00010000)
+
+/*******************************************************************************
+ * NS_BL1U specific defines.
+ * NS_BL1U RW data is relocated from NS-ROM to NS-RAM at runtime so we
+ * need 2 sets of addresses.
+ ******************************************************************************/
+#define NS_BL1U_RO_BASE		(0x08000000 + 0x03EB8000)
+#define NS_BL1U_RO_LIMIT	(NS_BL1U_RO_BASE + 0xC000)
+
+/*******************************************************************************
+ * Put NS_BL1U RW at the top of the Non-Trusted SRAM. NS_BL1U_RW_BASE is
+ * calculated using the current NS_BL1U RW debug size plus a little space
+ * for growth.
+ ******************************************************************************/
+#define NS_BL1U_RW_SIZE		(0x7000)
+#define NS_BL1U_RW_BASE		(NSRAM_BASE)
+#define NS_BL1U_RW_LIMIT	(NS_BL1U_RW_BASE + NS_BL1U_RW_SIZE)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define FVP_DRAM1_BASE			0x80000000
+#define FVP_DRAM2_BASE			0x880000000
+#define DRAM_BASE			FVP_DRAM1_BASE
+#define DRAM_SIZE			0x80000000
+
+/*******************************************************************************
+ * Base address and limit for NS_BL2U image.
+ ******************************************************************************/
+#define NS_BL2U_BASE		DRAM_BASE
+#define NS_BL2U_LIMIT		(NS_BL2U_BASE + 0x4D000)
+
+/******************************************************************************
+ * Memory mapped Generic timer interfaces
+ ******************************************************************************/
+/* REFCLK CNTControl, Generic Timer. Secure Access only. */
+#define SYS_CNT_CONTROL_BASE		0x2a430000
+/* REFCLK CNTRead, Generic Timer. */
+#define SYS_CNT_READ_BASE		0x2a800000
+/* AP_REFCLK CNTBase1, Generic Timer. */
+#define SYS_CNT_BASE1			0x2a830000
+
+/* V2M motherboard system registers & offsets */
+#define VE_SYSREGS_BASE		0x1c010000
+#define V2M_SYS_LED		0x8
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stacks */
+#if IMAGE_NS_BL1U || IMAGE_NS_BL2U
+#define PLATFORM_STACK_SIZE	0x1000
+#else
+#define PLATFORM_STACK_SIZE	0x1400
+#endif
+
+/* Size of coherent stacks for debug and release builds */
+#if DEBUG
+#define PCPU_DV_MEM_STACK_SIZE	0x600
+#else
+#define PCPU_DV_MEM_STACK_SIZE	0x500
+#endif
+
+#define PLATFORM_CORE_COUNT		(FVP_CLUSTER_COUNT * \
+						FVP_MAX_CPUS_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS		(1 + FVP_CLUSTER_COUNT + \
+					 PLATFORM_CORE_COUNT)
+#define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL2
+
+/* TODO : Migrate complete TFTF from affinity level to power levels */
+#define PLAT_MAX_PWR_LEVEL		PLATFORM_MAX_AFFLVL
+#define PLAT_MAX_PWR_STATES_PER_LVL	2
+
+#if IMAGE_NS_BL1U
+#define MAX_IO_DEVICES			2
+#define MAX_IO_HANDLES			2
+#else
+#define MAX_IO_DEVICES			1
+#define MAX_IO_HANDLES			1
+#endif
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH		4
+
+#if USE_NVM
+/*
+ * The Flash memory is used to store the TFTF data on FVP.
+ * However, it might contain other data that must not be overwritten.
+ * For example, when using the Trusted Firmware-A, the FIP image
+ * (containing the bootloader images) is also stored in Flash.
+ * Hence, consider the first 40MB of Flash as reserved for firmware usage.
+ * The TFTF can use the rest of the Flash memory.
+ */
+#define TFTF_NVM_OFFSET		0x2800000	/* 40 MB */
+#define TFTF_NVM_SIZE		(FLASH_SIZE - TFTF_NVM_OFFSET)
+#else
+/*
+ * If you want to run without support for non-volatile memory (due to
+ * e.g. unavailability of a flash driver), DRAM can be used instead as
+ * a workaround. The TFTF binary itself is loaded at 0x88000000 so the
+ * first 128MB can be used
+ * Please note that this won't be suitable for all test scenarios and
+ * for this reason some tests will be disabled in this configuration.
+ */
+#define TFTF_NVM_OFFSET		0x0
+#define TFTF_NVM_SIZE		(TFTF_BASE - DRAM_BASE - TFTF_NVM_OFFSET)
+#endif
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
+#if IMAGE_TFTF
+#define MAX_XLAT_TABLES			6
+#define MAX_MMAP_REGIONS		16
+#else
+#define MAX_XLAT_TABLES			5
+#define MAX_MMAP_REGIONS		16
+#endif
+
+/*******************************************************************************
+ * Used to align variables on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT		6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+/*******************************************************************************
+ * Non-Secure Software Generated Interupts IDs
+ ******************************************************************************/
+#define IRQ_NS_SGI_0			0
+#define IRQ_NS_SGI_1			1
+#define IRQ_NS_SGI_2			2
+#define IRQ_NS_SGI_3			3
+#define IRQ_NS_SGI_4			4
+#define IRQ_NS_SGI_5			5
+#define IRQ_NS_SGI_6			6
+#define IRQ_NS_SGI_7			7
+
+/*
+ * On FVP, consider that the last SPI is the Trusted Random Number Generator
+ * interrupt.
+ */
+#define PLAT_MAX_SPI_OFFSET_ID		107
+
+/* AP_REFCLK, Generic Timer, CNTPSIRQ1. */
+#define IRQ_CNTPSIRQ1			58
+/* Per-CPU Hypervisor Timer Interrupt ID */
+#define IRQ_PCPU_HP_TIMER		26
+/* Per-CPU Non-Secure Timer Interrupt ID */
+#define IRQ_PCPU_NS_TIMER		30
+
+
+/* Times(in ms) used by test code for completion of different events */
+#define PLAT_SUSPEND_ENTRY_TIME		15
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME	30
+
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/arm/fvp/plat_setup.c b/plat/arm/fvp/plat_setup.c
new file mode 100644
index 0000000..0d81686
--- /dev/null
+++ b/plat/arm/fvp/plat_setup.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arm_gic.h>
+#include <plat_arm.h>
+#include <platform.h>
+
+/*
+ * Table of regions to map using the MMU.
+ */
+#if IMAGE_NS_BL1U
+static const mmap_region_t mmap[] = {
+	MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(FLASH_BASE, FLASH_SIZE, MT_MEMORY | MT_RO | MT_NS),
+	MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+	{0}
+ };
+#elif IMAGE_NS_BL2U
+static const mmap_region_t mmap[] = {
+	MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+	{0}
+};
+#elif IMAGE_TFTF
+static const mmap_region_t mmap[] = {
+	MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_NS),
+	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
+#if USE_NVM
+	MAP_REGION_FLAT(FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS),
+#endif
+	MAP_REGION_FLAT(DRAM_BASE, TFTF_BASE - DRAM_BASE, MT_MEMORY | MT_RW | MT_NS),
+	{0}
+};
+#endif	/* IMAGE_NS_BL1U */
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+	return mmap;
+}
+
+void plat_arm_gic_init(void)
+{
+	arm_gic_init(GICC_BASE, GICD_BASE, GICR_BASE);
+}
diff --git a/plat/arm/fvp/platform.mk b/plat/arm/fvp/platform.mk
new file mode 100644
index 0000000..0230124
--- /dev/null
+++ b/plat/arm/fvp/platform.mk
@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2018, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_INCLUDES	:=	-Iplat/arm/fvp/include/
+
+PLAT_SOURCES	:=	drivers/arm/gic/arm_gic_v2v3.c			\
+			drivers/arm/gic/gic_v2.c			\
+			drivers/arm/gic/gic_v3.c			\
+			drivers/arm/sp805/sp805.c			\
+			drivers/arm/timer/private_timer.c		\
+			drivers/arm/timer/system_timer.c		\
+			plat/arm/fvp/${ARCH}/plat_helpers.S		\
+			plat/arm/fvp/fvp_pwr_state.c			\
+			plat/arm/fvp/fvp_topology.c			\
+			plat/arm/fvp/fvp_mem_prot.c			\
+			plat/arm/fvp/plat_setup.c
+
+CACTUS_SOURCES	+=	plat/arm/fvp/${ARCH}/plat_helpers.S
+
+# Firmware update is implemented on FVP.
+FIRMWARE_UPDATE := 1
+
+include plat/arm/common/arm_common.mk