feat(brbe): test that EL3 has properly enabled access to BRBE

Access to FEAT_BRBE control registers must be explicitly enabled in EL3,
this simple test just ensures that the registers are accessible or traps
to EL3, similar to the TRBE test.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0a25c5ce6beb6aa96b9428264b75cb3569ac535a

4 files changed, 43 insertions, 0 deletions

diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index a69eb72..e838270 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -309,6 +309,14 @@ typedef test_result_t (*test_function_arg_t)(void *arg);
 	} while (false)
 #endif
 
+#define SKIP_TEST_IF_BRBE_NOT_SUPPORTED()					\
+	do {									\
+		if (!get_feat_brbe_support()) {				\
+			tftf_testcase_printf("FEAT_BRBE not supported\n");	\
+			return TEST_RESULT_SKIPPED;				\
+		}								\
+	} while (false)
+
 /* Helper macro to verify if system suspend API is supported */
 #define is_psci_sys_susp_supported()	\
 		(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND)		\
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 399da93..dd0f899 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -167,6 +167,11 @@
 #define ID_AA64DFR0_V8_2_DEBUG_ARCH_SUPPORTED	U(8)
 #define ID_AA64DFR0_V8_4_DEBUG_ARCH_SUPPORTED	U(9)
 
+/* ID_AA64DFR0_EL1.BRBE definitions */
+#define ID_AA64DFR0_BRBE_SHIFT			U(52)
+#define ID_AA64DFR0_BRBE_MASK			ULL(0xf)
+#define ID_AA64DFR0_BRBE_SUPPORTED		ULL(1)
+
 /* ID_AA64DFR0_EL1.TraceBuffer definitions */
 #define ID_AA64DFR0_TRACEBUFFER_SHIFT		U(44)
 #define ID_AA64DFR0_TRACEBUFFER_MASK		ULL(0xf)
@@ -1114,6 +1119,19 @@
 #define TRBIDR_EL1	S3_0_C9_C11_7
 
 /*******************************************************************************
+ * FEAT_BRBE - Branch Record Buffer Extension System Registers
+ ******************************************************************************/
+
+#define BRBCR_EL1	S2_1_C9_C0_0
+#define BRBCR_EL2	S2_4_C9_C0_0
+#define BRBFCR_EL1	S2_1_C9_C0_1
+#define BRBTS_EL1	S2_1_C9_C0_2
+#define BRBINFINJ_EL1	S2_1_C9_C1_0
+#define BRBSRCINJ_EL1	S2_1_C9_C1_1
+#define BRBTGTINJ_EL1	S2_1_C9_C1_2
+#define BRBIDR0_EL1	S2_1_C9_C2_0
+
+/*******************************************************************************
  * Armv8.4 - Trace Filter System Registers
  ******************************************************************************/
 #define TRFCR_EL1	S3_0_C1_C2_1
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 4da6407..77b9f9d 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -154,4 +154,11 @@ static inline bool get_feat_afp_present(void)
 		  ID_AA64MMFR1_EL1_AFP_MASK) == ID_AA64MMFR1_EL1_AFP_SUPPORTED);
 }
 
+static inline bool get_feat_brbe_support(void)
+{
+	return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_BRBE_SHIFT) &
+		ID_AA64DFR0_BRBE_MASK) ==
+		ID_AA64DFR0_BRBE_SUPPORTED;
+}
+
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index eac8b7c..b6d924b 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -524,6 +524,16 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(trbmar_el1, TRBMAR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(trbtrg_el1, TRBTRG_EL1)
 DEFINE_RENAME_SYSREG_READ_FUNC(trbidr_el1, TRBIDR_EL1)
 
+/* FEAT_BRBE Branch record buffer extension system registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(brbcr_el1, BRBCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(brbcr_el2, BRBCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(brbfcr_el1, BRBFCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(brbts_el1, BRBTS_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(brbinfinj_el1, BRBINFINJ_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(brbsrcinj_el1, BRBSRCINJ_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(brbtgtinj_el1, BRBTGTINJ_EL1)
+DEFINE_RENAME_SYSREG_READ_FUNC(brbidr0_el1, BRBIDR0_EL1)
+
 /* Armv8.4 Trace filter control System Registers */
 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)