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authorBipin Ravi <bipin.ravi@arm.com>2022-05-18 22:03:20 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2022-05-18 22:03:20 +0200
commit76c458a1fd6318f9d8fd7ab142985389d6b7db78 (patch)
treeafca4415b1d63c0c2378895f7cf14fb6c5bb4861 /include
parentcf67732e659b35777459456a495cdf03ca875101 (diff)
parentb31bc759af589bc95e3a88bbe5b525ad84d1ac89 (diff)
Merge "feat(WFxT): add a test for WFxT instructions"
Diffstat (limited to 'include')
-rw-r--r--include/common/test_helpers.h10
-rw-r--r--include/lib/aarch64/arch.h6
-rw-r--r--include/lib/aarch64/arch_features.h13
-rw-r--r--include/lib/aarch64/arch_helpers.h14
4 files changed, 38 insertions, 5 deletions
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index 7a14079..c808df1 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -293,7 +293,7 @@ typedef test_result_t (*test_function_arg_t)(void *arg);
#define SKIP_TEST_IF_AFP_NOT_SUPPORTED() \
do { \
if (!get_feat_afp_present()) { \
- tftf_testcase_printf("ARMv8.7-afp not supported"); \
+ tftf_testcase_printf("ARMv8.7-afp not supported\n"); \
return TEST_RESULT_SKIPPED; \
} \
} while (false)
@@ -325,6 +325,14 @@ typedef test_result_t (*test_function_arg_t)(void *arg);
} \
} while (false)
+#define SKIP_TEST_IF_WFXT_NOT_SUPPORTED() \
+ do { \
+ if (!get_feat_wfxt_present()) { \
+ tftf_testcase_printf("ARMv8.7-WFxT not supported\n"); \
+ return TEST_RESULT_SKIPPED; \
+ } \
+ } while (false)
+
/* Helper macro to verify if system suspend API is supported */
#define is_psci_sys_susp_supported() \
(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND) \
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index dd0f899..c5c94fb 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -210,6 +210,12 @@
#define ID_AA64ISAR1_APA_WIDTH U(4)
#define ID_AA64ISAR1_APA_MASK ULL(0xf)
+/* ID_AA64ISAR2_EL1 definitions */
+#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
+#define ID_AA64ISAR2_WFXT_MASK ULL(0xf)
+#define ID_AA64ISAR2_WFXT_SHIFT U(0x0)
+#define ID_AA64ISAR2_WFXT_SUPPORTED ULL(0x2)
+
/* ID_AA64MMFR0_EL1 definitions */
#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 77b9f9d..46d12c9 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -8,7 +8,6 @@
#define ARCH_FEATURES_H
#include <stdbool.h>
-
#include <arch_helpers.h>
static inline bool is_armv7_gentimer_present(void)
@@ -112,21 +111,21 @@ static inline uint32_t arch_get_debug_version(void)
static inline bool get_armv9_0_trbe_support(void)
{
- return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT) &
+ return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT) &
ID_AA64DFR0_TRACEBUFFER_MASK) ==
ID_AA64DFR0_TRACEBUFFER_SUPPORTED;
}
static inline bool get_armv8_4_trf_support(void)
{
- return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT) &
+ return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT) &
ID_AA64DFR0_TRACEFILT_MASK) ==
ID_AA64DFR0_TRACEFILT_SUPPORTED;
}
static inline bool get_armv8_0_sys_reg_trace_support(void)
{
- return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEVER_SHIFT) &
+ return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEVER_SHIFT) &
ID_AA64DFR0_TRACEVER_MASK) ==
ID_AA64DFR0_TRACEVER_SUPPORTED;
}
@@ -161,4 +160,10 @@ static inline bool get_feat_brbe_support(void)
ID_AA64DFR0_BRBE_SUPPORTED;
}
+static inline bool get_feat_wfxt_present(void)
+{
+ return (((read_id_aa64isar2_el1() >> ID_AA64ISAR2_WFXT_SHIFT) &
+ ID_AA64ISAR2_WFXT_MASK) == ID_AA64ISAR2_WFXT_SUPPORTED);
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index b6d924b..b366cdd 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -75,6 +75,13 @@ static inline void _op ## _type(void) \
__asm__ (#_op " " #_type); \
}
+/* Define function for system instruction with register with variable parameter */
+#define DEFINE_SYSOP_PARAM_FUNC(_op) \
+static inline void _op(uint64_t v) \
+{ \
+ __asm__ (#_op " " "%0" : : "r" (v)); \
+}
+
/* Define function for system instruction with register parameter */
#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
static inline void _op ## _type(uint64_t v) \
@@ -199,6 +206,7 @@ DEFINE_SYSREG_RW_FUNCS(elr_el3)
DEFINE_SYSOP_FUNC(wfi)
DEFINE_SYSOP_FUNC(wfe)
DEFINE_SYSOP_FUNC(sev)
+DEFINE_SYSOP_FUNC(sevl)
DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
DEFINE_SYSOP_TYPE_FUNC(dmb, st)
@@ -217,6 +225,9 @@ DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
DEFINE_SYSOP_FUNC(isb)
+DEFINE_SYSOP_PARAM_FUNC(wfit)
+DEFINE_SYSOP_PARAM_FUNC(wfet)
+
static inline void enable_irq(void)
{
/*
@@ -557,6 +568,9 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
/* Control floating point behaviour */
DEFINE_RENAME_SYSREG_RW_FUNCS(fpcr, FPCR)
+/* ID_AA64ISAR2_EL1 */
+DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
+
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)