diff options
| author | Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> | 2023-01-16 17:58:47 +0000 |
|---|---|---|
| committer | Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> | 2023-04-28 00:51:01 +0100 |
| commit | 95d5d2764c2f44b06af709dd093e9ff0f17ced14 (patch) | |
| tree | b0d3d8d67c94521b107522dac8631e13bc90b9f8 /include/lib/aarch64 | |
| parent | b3ffd3c17ea83c48a90d7165ab5c5140540bc81f (diff) | |
feat(sme): add basic SME2 tests
FEAT_SME2 introduces an architectural register ZT0 to support
lookup table feature. This patch ensures that EL3 has
properly enabled the SME2 for use at lower exception levels,
thereby disabling the traps execution at lower exception levels,
when instructions access ZT0 register to EL3.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I46d51184b74c1e82c88344530601f2a3c1aee8ea
Diffstat (limited to 'include/lib/aarch64')
| -rw-r--r-- | include/lib/aarch64/arch.h | 2 | ||||
| -rw-r--r-- | include/lib/aarch64/arch_features.h | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 2f4b0c9..1cbe3c3 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -332,6 +332,7 @@ #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) +#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) @@ -887,6 +888,7 @@ /* SMCR_ELx definitions */ #define SMCR_ELX_LEN_SHIFT U(0) #define SMCR_ELX_LEN_MASK U(0x1ff) +#define SMCR_ELX_EZT0_BIT (U(1) << 30) #define SMCR_ELX_FA64_BIT (U(1) << 31) /******************************************************************************* diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h index bb1d156..203d140 100644 --- a/include/lib/aarch64/arch_features.h +++ b/include/lib/aarch64/arch_features.h @@ -232,4 +232,12 @@ static inline bool is_feat_sme_fa64_supported(void) return (features & ID_AA64SMFR0_EL1_FA64_BIT) != 0U; } +static inline bool is_feat_sme2_supported(void) +{ + uint64_t features; + + features = read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SME_SHIFT; + return (features & ID_AA64PFR1_EL1_SME_MASK) >= ID_AA64PFR1_EL1_SME2_SUPPORTED; +} + #endif /* ARCH_FEATURES_H */ |