diff options
| author | Olivier Deprez <olivier.deprez@arm.com> | 2022-12-06 10:36:14 +0100 |
|---|---|---|
| committer | Olivier Deprez <olivier.deprez@arm.com> | 2022-12-06 10:39:39 +0100 |
| commit | 29acc7dc064d259c37ccadaab88276dce03c242f (patch) | |
| tree | 0d322dd58c7c9fee6ff73aabf58b7b41c7eccbd6 | |
| parent | 4ca852f826e4b1e43739493c4d0916a426a8722a (diff) | |
fix: cactus entry point get core linear id
In the cactus entry point there is remnant call to the platform specific
physical MPIDR to linear id conversion routine. This is incorrect
because S-EL1 read of MPIDR is emulated by the SPMC and returns the vCPU
linear id rather than the physical MPIDR.
Add a check that the core linear id inferred by MPIDR is matching the id
passed by the SPMC through x4. This feature was added to support legacy
TEEs expecting the core linear id to be passed by TF-A.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I6902e8f06ab6c79953f6891e582fc8975825a6c4
| -rw-r--r-- | spm/cactus/aarch64/cactus_entrypoint.S | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/spm/cactus/aarch64/cactus_entrypoint.S b/spm/cactus/aarch64/cactus_entrypoint.S index 6eff65e..17f0798 100644 --- a/spm/cactus/aarch64/cactus_entrypoint.S +++ b/spm/cactus/aarch64/cactus_entrypoint.S @@ -20,22 +20,33 @@ stacks_end: func cactus_entrypoint /* Entry reason is primary EC cold boot */ mov x19, #1 + + /* Fall-through. */ + secondary_cold_entry: /* + * Entry reason is secondary EC cold boot (or primary EC cold + * boot from above). + */ + + /* * x0 holds a pointer to the Boot Information Blob. * Save it for later usage. */ mov x20, x0 - /* Get the vMPIDR. The SPMC passes the vCPU linear id in lower bits. */ + /* The SPMC passes the vCPU id in vMPIDR low bits. */ mrs x0, mpidr_el1 bic x0, x0, #0x80000000 - /* Entry reason is secondary EC cold boot */ - mrs x0, mpidr_el1 - bl platform_get_core_pos + /* + * To maintain legacy, the SPMC passes the physical core id through x4. + * For a MP SP check the physical core id matches the vCPU id. + */ + cmp x4, x0 + bne . - /* Setup the stack pointer. */ + /* Setup the stack pointer (from the linear id stored in x0). */ adr x1, stacks_end mov x2, #SP_STACKS_SIZE mul x2, x0, x2 |