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authorManish Pandey <manish.pandey2@arm.com>2021-03-02 14:41:58 +0000
committerOlivier Deprez <olivier.deprez@arm.com>2021-04-13 18:23:29 +0200
commitd27b37d7543a8cf0f78e875de7510064a9882de7 (patch)
tree5766b0888b3a3fe1f56a74220c7db73e1243467d
parent6967c24a7616326c0bb8cf57873a2788523d37d2 (diff)
Cactus: decouple exception handling from tftf framework
So far, tftf framework's exception handling was used for Cactus exceptions also. With new interrupt related tests coming up in Cactus, we need a separate exception handler code for Cactus. This patch enables irq/fiq for Cactus and adds placeholder handlers for them. Change-Id: Ifd89c4ba8b4491345948bf342540b37fdbc91b8d Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
-rw-r--r--spm/cactus/aarch64/cactus_entrypoint.S4
-rw-r--r--spm/cactus/aarch64/cactus_exceptions.S131
-rw-r--r--spm/cactus/cactus.mk3
-rw-r--r--spm/cactus/cactus_interrupt.c32
-rw-r--r--spm/cactus/cactus_main.c4
5 files changed, 171 insertions, 3 deletions
diff --git a/spm/cactus/aarch64/cactus_entrypoint.S b/spm/cactus/aarch64/cactus_entrypoint.S
index 7e63856..b52aa38 100644
--- a/spm/cactus/aarch64/cactus_entrypoint.S
+++ b/spm/cactus/aarch64/cactus_entrypoint.S
@@ -49,8 +49,8 @@ secondary_cold_entry:
isb
/* Set up exceptions vector table */
- adrp x1, tftf_vector
- add x1, x1, :lo12:tftf_vector
+ adrp x1, cactus_vector
+ add x1, x1, :lo12:cactus_vector
msr vbar_el1, x1
isb
diff --git a/spm/cactus/aarch64/cactus_exceptions.S b/spm/cactus/aarch64/cactus_exceptions.S
new file mode 100644
index 0000000..31cdbf9
--- /dev/null
+++ b/spm/cactus/aarch64/cactus_exceptions.S
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+
+ .globl cactus_vector
+
+/*
+ * Exception vector code for unhandled exceptions.
+ * Print a crash dump on the UART and loops forever.
+ */
+.macro unhandled_exception name
+ vector_entry \name
+ b crash_dump
+ end_vector_entry \name
+.endm
+
+vector_base cactus_vector
+
+ /*
+ * Current EL with SP0 : 0x0 - 0x200.
+ */
+unhandled_exception sync_sp0
+unhandled_exception irq_sp0
+unhandled_exception fiq_sp0
+unhandled_exception serr_sp0
+
+ /*
+ * Current EL with SPx : 0x200 - 0x400.
+ */
+unhandled_exception sync_spx
+
+vector_entry irq_spx
+ b irq_vector_entry
+end_vector_entry irq_spx
+
+vector_entry fiq_spx
+ b fiq_vector_entry
+end_vector_entry fiq_spx
+
+unhandled_exception serr_spx
+
+ /*
+ * Lower EL using AArch64 : 0x400 - 0x600.
+ */
+unhandled_exception sync_a64
+unhandled_exception irq_a64
+unhandled_exception fiq_a64
+unhandled_exception serr_a64
+
+ /*
+ * Lower EL using AArch32 : 0x600 - 0x800.
+ */
+unhandled_exception sync_a32
+unhandled_exception irq_a32
+unhandled_exception fiq_a32
+unhandled_exception serr_a32
+
+.macro save_gp_regs
+ stp x0, x1, [sp, #0x0]
+ stp x2, x3, [sp, #0x10]
+ stp x4, x5, [sp, #0x20]
+ stp x6, x7, [sp, #0x30]
+ stp x8, x9, [sp, #0x40]
+ stp x10, x11, [sp, #0x50]
+ stp x12, x13, [sp, #0x60]
+ stp x14, x15, [sp, #0x70]
+ stp x16, x17, [sp, #0x80]
+ stp x18, x19, [sp, #0x90]
+ stp x20, x21, [sp, #0xa0]
+ stp x22, x23, [sp, #0xb0]
+ stp x24, x25, [sp, #0xc0]
+ stp x26, x27, [sp, #0xd0]
+ stp x28, x29, [sp, #0xe0]
+ /* We push xzr simply to keep the stack 16-byte aligned. */
+ stp x30, xzr, [sp, #0xf0]
+.endm
+
+.macro restore_gp_regs
+ ldp x30, xzr, [sp, #0xf0]
+ ldp x28, x29, [sp, #0xe0]
+ ldp x26, x27, [sp, #0xd0]
+ ldp x24, x25, [sp, #0xc0]
+ ldp x22, x23, [sp, #0xb0]
+ ldp x20, x21, [sp, #0xa0]
+ ldp x18, x19, [sp, #0x90]
+ ldp x16, x17, [sp, #0x80]
+ ldp x14, x15, [sp, #0x70]
+ ldp x12, x13, [sp, #0x60]
+ ldp x10, x11, [sp, #0x50]
+ ldp x8, x9, [sp, #0x40]
+ ldp x6, x7, [sp, #0x30]
+ ldp x4, x5, [sp, #0x20]
+ ldp x2, x3, [sp, #0x10]
+ ldp x0, x1, [sp, #0x0]
+.endm
+
+func irq_vector_entry
+ sub sp, sp, #0x100
+ save_gp_regs
+ bl cactus_irq_handler
+ restore_gp_regs
+ add sp, sp, #0x100
+ eret
+endfunc irq_vector_entry
+
+func fiq_vector_entry
+ sub sp, sp, #0x100
+ save_gp_regs
+ bl cactus_fiq_handler
+ restore_gp_regs
+ add sp, sp, #0x100
+ eret
+endfunc fiq_vector_entry
+
+func crash_dump
+ /* Save general-purpose registers on the stack. */
+ sub sp, sp, #0x100
+ save_gp_regs
+
+ /* Save original stack pointer value on the stack. */
+ add x1, sp, #0x100
+ str x1, [sp, #0xf8]
+
+ /* Print the saved CPU context on the UART. */
+ mov x0, sp
+ b print_exception
+endfunc crash_dump
diff --git a/spm/cactus/cactus.mk b/spm/cactus/cactus.mk
index 9d47b90..70961eb 100644
--- a/spm/cactus/cactus.mk
+++ b/spm/cactus/cactus.mk
@@ -32,7 +32,9 @@ CACTUS_INCLUDES := \
CACTUS_SOURCES := \
$(addprefix spm/cactus/, \
aarch64/cactus_entrypoint.S \
+ aarch64/cactus_exceptions.S \
cactus_debug.c \
+ cactus_interrupt.c \
cactus_main.c \
) \
$(addprefix spm/common/, \
@@ -54,7 +56,6 @@ CACTUS_SOURCES += \
tftf/framework/${ARCH}/asm_debug.S \
tftf/tests/runtime_services/secure_service/ffa_helpers.c \
tftf/tests/runtime_services/secure_service/spm_common.c \
- tftf/framework/${ARCH}/exceptions.S \
tftf/framework/${ARCH}/exception_report.c
CACTUS_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S \
diff --git a/spm/cactus/cactus_interrupt.c b/spm/cactus/cactus_interrupt.c
new file mode 100644
index 0000000..c7ad269
--- /dev/null
+++ b/spm/cactus/cactus_interrupt.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+
+#include <ffa_helpers.h>
+#include <sp_helpers.h>
+
+int cactus_irq_handler(void)
+{
+ uint32_t irq_num;
+
+ irq_num = spm_interrupt_get();
+
+ ERROR("%s: Interrupt ID %u not handled!\n", __func__, irq_num);
+
+ return 0;
+}
+
+int cactus_fiq_handler(void)
+{
+ uint32_t fiq_num;
+
+ fiq_num = spm_interrupt_get();
+
+ ERROR("%s: Interrupt ID %u not handled!\n", __func__, fiq_num);
+
+ return 0;
+}
diff --git a/spm/cactus/cactus_main.c b/spm/cactus/cactus_main.c
index ed48fe4..8cd57e7 100644
--- a/spm/cactus/cactus_main.c
+++ b/spm/cactus/cactus_main.c
@@ -197,6 +197,10 @@ void __dead2 cactus_main(bool primary_cold_boot)
enable_mmu_el1(0);
+ /* Enable IRQ/FIQ */
+ enable_irq();
+ enable_fiq();
+
if (primary_cold_boot == false) {
goto msg_loop;
}