diff options
author | James Liao <jamesjj.liao@mediatek.com> | 2014-12-04 13:42:47 +0800 |
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committer | Vincent Guittot <vincent.guittot@linaro.org> | 2015-04-16 11:53:15 +0200 |
commit | 195a4e78b86aa0a7d0d7ee94b22cf4fdeec250b4 (patch) | |
tree | 627403312143391d204457378ec04f806c4eab8d /Documentation | |
parent | 019f6d370e597bda1b6af5fc3454bc14ccba651e (diff) |
clk: dts: mediatek: add Mediatek MT8135 clock bindings
Document the device-tree binding of Mediatek MT8135 SoC, including
TOPCKGEN, PLLs, INFRA and PERI clock controller.
Change-Id: Ie9175adebdb2d3b6aa1854d3bc11c57c191b3255
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/clock/mediatek,mt8135-clock.txt | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8135-clock.txt b/Documentation/devicetree/bindings/clock/mediatek,mt8135-clock.txt new file mode 100644 index 000000000000..1e3566fa0ea0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8135-clock.txt @@ -0,0 +1,44 @@ +Mediatek MT8135 Clock Controller + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The Mediatek MT8135 clock controller generates and supplies clock to various +controllers within Mediatek MT8135 SoC. + +Required Properties: + +- compatible: should be one of following: + - "mediatek,mt8135-topckgen" : for topckgen clock controller of MT8135. + - "mediatek,mt8135-apmixedsys" : for apmixed_sys (PLLs) of MT8135. + - "mediatek,mt8135-infracfg" : for infra_sys clock controller of MT8135. + - "mediatek,mt8135-pericfg" : for peri_sys clock controller of MT8135. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/mt8135-clk.h header and can be used in device tree sources. + +Example: I2C controller node that consumes the clock generated by the clock + controller (refer to the standard clock bindings for information about + "clocks" and "clock-names" properties): + + pericfg: pericfg@10003000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt8135-pericfg"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + i2c0: i2c@1100d000 { + compatible = "mediatek,mt8135-i2c", "mediatek,mt6589-i2c"; + reg = <0 0x1100d000 0 0x70>, <0 0x11000300 0 0x80>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; + clock-div = <16>; + clocks = <&pericfg PERI_I2C0_CK>, <&pericfg PERI_AP_DMA_CK>; + clock-names = "main", "dma"; + }; |