refactor(plat/sgi): header files and macros

In preparation to add support for the latest Neoverse reference design
platforms, reorganize the header files to allow newer platforms to use a
different set of platform macros. In addition to this, rename the macros
to match the names used in trusted firmware.

Signed-off-by: Shriram K <shriram.k@arm.com>
Change-Id: Ic21601730650d59ed8e40f763a0d5c4a5c45d3a3

9 files changed, 141 insertions, 75 deletions

diff --git a/plat/arm/sgi/common/aarch64/plat_helpers.S b/plat/arm/sgi/common/aarch64/plat_helpers.S
index 9fe2ba9..e17c509 100644
--- a/plat/arm/sgi/common/aarch64/plat_helpers.S
+++ b/plat/arm/sgi/common/aarch64/plat_helpers.S
@@ -18,13 +18,13 @@
  *
  * Function to calculate the core position on sgi platforms.
  *
- * (ClusterId * SGI_MAX_CPUS_PER_CLUSTER * SGI_MAX_PE_PER_CPU) +
- * (CPUId * SGI_MAX_PE_PER_CPU) +
+ * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
+ * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
  * ThreadId
  *
  * which can be simplified as:
  *
- * ((ClusterId * SGI_MAX_CPUS_PER_CLUSTER + CPUId) * SGI_MAX_PE_PER_CPU)
+ * ((ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER + CPUId) * CSS_SGI_MAX_PE_PER_CPU)
  * + ThreadId
  * ---------------------------------------------------------------------
  */
@@ -43,9 +43,9 @@ func platform_get_core_pos
 	ubfx	x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
 
 	/* Compute linear position */
-	mov	x3, #SGI_MAX_CPUS_PER_CLUSTER
+	mov	x3, #CSS_SGI_MAX_CPUS_PER_CLUSTER
 	madd	x1, x2, x3, x1
-	mov	x3, #SGI_MAX_PE_PER_CPU
+	mov	x3, #CSS_SGI_MAX_PE_PER_CPU
 	madd	x0, x1, x3, x0
 	ret
 endfunc platform_get_core_pos
diff --git a/plat/arm/sgi/common/include/sgi_base_platform_def.h b/plat/arm/sgi/common/include/sgi_base_platform_def.h
index 868f0e4..10d1841 100644
--- a/plat/arm/sgi/common/include/sgi_base_platform_def.h
+++ b/plat/arm/sgi/common/include/sgi_base_platform_def.h
@@ -7,35 +7,52 @@
 #ifndef SGI_BASE_PLATFORM_DEF_H
 #define SGI_BASE_PLATFORM_DEF_H
 
+#include <lib/utils_def.h>
+
 /* Platform binary types for linking */
 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
 #define PLATFORM_LINKER_ARCH		aarch64
 
-/*******************************************************************************
- * Run-time address of the TFTF image.
- * It has to match the location where the Trusted Firmware-A loads the BL33
- * image.
- ******************************************************************************/
-#define TFTF_BASE			0xE0000000
+/* Sub-system Peripherals */
+#define SGI_DEVICE0_BASE		UL(0x2A000000)
+#define SGI_DEVICE0_SIZE		UL(0x26000000)
 
-#define SGI_DRAM1_BASE			0x80000000
-#define SGI_DRAM1_SIZE			0x80000000
-#define DRAM_BASE			SGI_DRAM1_BASE
+/* Peripherals and PCIe expansion area */
+#define SGI_DEVICE1_BASE		UL(0x60000000)
+#define SGI_DEVICE1_SIZE		UL(0x20000000)
 
-/* TF-A reserves DRAM space 0xFF000000- 0xFFFFFFFF for TZC */
-#define DRAM_SIZE			(SGI_DRAM1_SIZE - 0x1000000)
+/* AP Non-Secure UART related constants */
+#define SGI_CSS_NSEC_UART_BASE		UL(0x2A400000)
+#define SGI_CSS_NSEC_CLK_IN_HZ		7372800
+
+#define PLAT_ARM_UART_BASE		SGI_CSS_NSEC_UART_BASE
+#define PLAT_ARM_UART_CLK_IN_HZ		SGI_CSS_NSEC_CLK_IN_HZ
+
+/* Base address of trusted watchdog (SP805) */
+#define SP805_TWDOG_BASE		UL(0x2A480000)
 
 /* Memory mapped Generic timer interfaces */
-#define SYS_CNT_BASE1			0x2A830000
+#define SYS_CNT_BASE1			UL(0x2A830000)
 
-/* Base address of non-trusted watchdog (SP805) */
-#define SP805_WDOG_BASE			0x1C0F0000
+/* DRAM base address and size */
+#define PLAT_ARM_DRAM1_BASE		UL(0x80000000)
+#define PLAT_ARM_DRAM1_SIZE		UL(0x80000000)
+#define DRAM_BASE			PLAT_ARM_DRAM1_BASE
+
+/* TF-A reserves DRAM space 0xFF000000- 0xFFFFFFFF for TZC */
+#define DRAM_SIZE			(PLAT_ARM_DRAM1_SIZE - 0x1000000)
 
 /* Base address and size of external NVM flash */
-#define FLASH_BASE			0x08000000
+#define FLASH_BASE			UL(0x08000000)
+#define FLASH_SIZE			UL(0x04000000)  /* 64MB */
+#define NOR_FLASH_BLOCK_SIZE		UL(0x40000)     /* 256KB */
 
-#define NOR_FLASH_BLOCK_SIZE		0x40000		/* 256KB */
-#define FLASH_SIZE			0x4000000	/* 64MB */
+/*******************************************************************************
+ * Run-time address of the TFTF image.
+ * It has to match the location where the Trusted Firmware-A loads the BL33
+ * image.
+ ******************************************************************************/
+#define TFTF_BASE			UL(0xE0000000)
 
 /*
  * If you want to use DRAM for non-volatile memory then the first 128MB
@@ -43,27 +60,7 @@
  * suitable since the state will be lost.
  */
 #define TFTF_NVM_OFFSET			0x0
-#define TFTF_NVM_SIZE			0x8000000	/* 128 MB */
-
-/* Sub-system Peripherals */
-#define SGI_DEVICE0_BASE		0x2A000000
-#define SGI_DEVICE0_SIZE		0x26000000
-
-/* Following covers Peripherals and PCIe expansion area */
-#define SGI_DEVICE1_BASE		0x60000000
-#define SGI_DEVICE1_SIZE		0x20000000
-
-/* GIC-600 & interrupt handling related constants */
-#define SGI_GICD_BASE			0x30000000
-#define SGI_GICR_BASE			0x300C0000
-#define SGI_GICC_BASE			0x2C000000
-
-/* SoC's PL011 UART0 related constants */
-#define SGI_PL011_UART0_BASE		UL(0x2A410000)
-#define SGI_PL011_UART0_CLK_IN_HZ	7372800
-
-#define PLAT_ARM_UART_BASE		SGI_PL011_UART0_BASE
-#define PLAT_ARM_UART_CLK_IN_HZ		SGI_PL011_UART0_CLK_IN_HZ
+#define TFTF_NVM_SIZE			UL(0x08000000)	/* 128 MB */
 
 /* Size of cacheable stacks */
 #define PLATFORM_STACK_SIZE		0x1400
@@ -71,23 +68,18 @@
 /* Size of coherent stacks */
 #define PCPU_DV_MEM_STACK_SIZE		0x600
 
-#define PLATFORM_CORE_COUNT		(SGI_CLUSTER_COUNT * SGI_MAX_CPUS_PER_CLUSTER)
-#define PLATFORM_NUM_AFFS		(SGI_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define PLATFORM_CORE_COUNT		(PLAT_ARM_CLUSTER_COUNT * \
+						CSS_SGI_MAX_CPUS_PER_CLUSTER)
+#define PLATFORM_NUM_AFFS		(PLAT_ARM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
 #define PLATFORM_MAX_AFFLVL		MPIDR_AFFLVL1
 
 #define PLAT_MAX_PWR_LEVEL		PLATFORM_MAX_AFFLVL
 #define PLAT_MAX_PWR_STATES_PER_LVL	2
 
-/* I/O Storage NOR flash device */
-#define MAX_IO_DEVICES			1
-#define MAX_IO_HANDLES			1
-
 /* Local state bit width for each level in the state-ID field of power state */
 #define PLAT_LOCAL_PSTATE_WIDTH		4
 
 /* Platform specific page table and MMU setup constants */
-#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
 #define MAX_XLAT_TABLES			5
 #define MAX_MMAP_REGIONS		16
 
@@ -96,24 +88,22 @@
  * This is known only to the platform as it might have a combination of
  * integrated and external caches.
  ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT  		 6
-#define CACHE_WRITEBACK_GRANULE		 (1 << CACHE_WRITEBACK_SHIFT)
+#define CACHE_WRITEBACK_SHIFT		6
+#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+
+/* Times(in ms) used by test code for completion of different events */
+#define PLAT_SUSPEND_ENTRY_TIME		15
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME	30
+
+/* I/O Storage NOR flash device */
+#define MAX_IO_DEVICES			1
+#define MAX_IO_HANDLES			1
 
 /* Non-Secure Software Generated Interupts IDs */
 #define IRQ_NS_SGI_0			0
 #define IRQ_NS_SGI_7			7
 
-/* AP UART1 interrupt is considered as the maximum SPI */
-#define PLAT_MAX_SPI_OFFSET_ID		64
-
-/* AP_REFCLK Generic Timer, Non-secure. */
-#define IRQ_CNTPSIRQ1			92
-
 /* Per-CPU Hypervisor Timer Interrupt ID */
 #define IRQ_PCPU_HP_TIMER		26
 
-/* Times(in ms) used by test code for completion of different events */
-#define PLAT_SUSPEND_ENTRY_TIME		15
-#define PLAT_SUSPEND_ENTRY_EXIT_TIME	30
-
 #endif /* SGI_BASE_PLATFORM_DEF_H */
diff --git a/plat/arm/sgi/common/include/sgi_soc_css_def.h b/plat/arm/sgi/common/include/sgi_soc_css_def.h
new file mode 100644
index 0000000..da73b3e
--- /dev/null
+++ b/plat/arm/sgi/common/include/sgi_soc_css_def.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SOC_CSS_DEF_H
+#define SGI_SOC_CSS_DEF_H
+
+/* Trusted watchdog (SP805) Interrupt ID */
+#define IRQ_TWDOG_INTID			86
+
+/* Maximum SPI */
+#define PLAT_MAX_SPI_OFFSET_ID		64
+
+/* AP_REFCLK Generic Timer, Non-secure. */
+#define IRQ_CNTPSIRQ1			92
+
+#endif /* SGI_SOC_CSS_DEF_H */
diff --git a/plat/arm/sgi/common/include/sgi_soc_css_def_v2.h b/plat/arm/sgi/common/include/sgi_soc_css_def_v2.h
new file mode 100644
index 0000000..e834386
--- /dev/null
+++ b/plat/arm/sgi/common/include/sgi_soc_css_def_v2.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SOC_CSS_DEF_V2_H
+#define SGI_SOC_CSS_DEF_V2_H
+
+/* Trusted watchdog (SP805) Interrupt ID */
+#define IRQ_TWDOG_INTID			107
+
+/* Maximum SPI */
+#define PLAT_MAX_SPI_OFFSET_ID		256
+
+/* AP_REFCLK Generic Timer, Non-secure. */
+#define IRQ_CNTPSIRQ1			109
+
+#endif /* SGI_SOC_CSS_DEF_V2_H */
+
diff --git a/plat/arm/sgi/common/include/sgi_soc_platform_def.h b/plat/arm/sgi/common/include/sgi_soc_platform_def.h
new file mode 100644
index 0000000..fc60999
--- /dev/null
+++ b/plat/arm/sgi/common/include/sgi_soc_platform_def.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SOC_PLATFORM_H
+#define SGI_SOC_PLATFORM_H
+
+#include <sgi_base_platform_def.h>
+#include <sgi_soc_css_def.h>
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE		UL(0x1C0F0000)
+
+#endif /*  SGI_SOC_PLATFORM_H */
diff --git a/plat/arm/sgi/common/include/sgi_soc_platform_def_v2.h b/plat/arm/sgi/common/include/sgi_soc_platform_def_v2.h
new file mode 100644
index 0000000..fad31ca
--- /dev/null
+++ b/plat/arm/sgi/common/include/sgi_soc_platform_def_v2.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SOC_PLATFORM_V2_H
+#define SGI_SOC_PLATFORM_V2_H
+
+#include <sgi_base_platform_def.h>
+#include <sgi_soc_css_def_v2.h>
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE		UL(0x0C0F0000)
+
+#endif /*  SGI_SOC_PLATFORM_V2_H */
diff --git a/plat/arm/sgi/common/plat_setup.c b/plat/arm/sgi/common/plat_setup.c
index 4b15f1a..f343f8d 100644
--- a/plat/arm/sgi/common/plat_setup.c
+++ b/plat/arm/sgi/common/plat_setup.c
@@ -24,5 +24,5 @@ const mmap_region_t *tftf_platform_get_mmap(void)
 
 void plat_arm_gic_init(void)
 {
-	arm_gic_init(SGI_GICC_BASE, SGI_GICD_BASE, SGI_GICR_BASE);
+	arm_gic_init(PLAT_ARM_GICC_BASE, PLAT_ARM_GICD_BASE, PLAT_ARM_GICR_BASE);
 }
diff --git a/plat/arm/sgi/sgi575/include/platform_def.h b/plat/arm/sgi/sgi575/include/platform_def.h
index 1e5aff5..237978c 100644
--- a/plat/arm/sgi/sgi575/include/platform_def.h
+++ b/plat/arm/sgi/sgi575/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,14 +7,19 @@
 #ifndef PLATFORM_DEF_H
 #define PLATFORM_DEF_H
 
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
 
-#define SGI_CLUSTER_COUNT		2
-#define SGI_MAX_CPUS_PER_CLUSTER	4
-#define SGI_MAX_PE_PER_CPU		1
+#define PLAT_ARM_CLUSTER_COUNT		U(2)
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER	U(4)
+#define CSS_SGI_MAX_PE_PER_CPU		U(1)
 
-/* Base address of trusted watchdog (SP805) */
-#define SP805_TWDOG_BASE		0x2A480000
-#define IRQ_TWDOG_INTID			86
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE		UL(0x30000000)
+#define PLAT_ARM_GICC_BASE		UL(0x2C000000)
+#define PLAT_ARM_GICR_BASE		UL(0x300C0000)
+
+/* Platform specific page table and MMU setup constants */
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
 
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/sgi/sgi575/sgi575_topology.c b/plat/arm/sgi/sgi575/sgi575_topology.c
index bda06d3..c01ad83 100644
--- a/plat/arm/sgi/sgi575/sgi575_topology.c
+++ b/plat/arm/sgi/sgi575/sgi575_topology.c
@@ -32,11 +32,11 @@ static const struct {
  */
 const unsigned char sgi575_pd_tree_desc[] = {
 	/* Number of root nodes */
-	SGI_CLUSTER_COUNT,
+	PLAT_ARM_CLUSTER_COUNT,
 	/* Number of children for the 1st node */
-	SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
 	/* Number of children for the 2nd node */
-	SGI_MAX_CPUS_PER_CLUSTER
+	CSS_SGI_MAX_CPUS_PER_CLUSTER
 };
 
 const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)