diff options
author | Joanna Farley <joanna.farley@arm.com> | 2023-09-19 14:49:16 +0200 |
---|---|---|
committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2023-09-19 14:49:16 +0200 |
commit | 6d8721db1753e0b9fc4252308186d5eb152252a8 (patch) | |
tree | 4464d81a42505c45e15b29820533bbf2ea0f894a | |
parent | e3c73d226e7a0edafdc49f4be9f5621f5d286454 (diff) | |
parent | 30b8bc2aadb82281da999c7264f399d2b7775c42 (diff) |
Merge changes from topic "xlnx_versal_net_intro"
* changes:
docs(versal-net): add Versal NET documentation
chore(xilinx): reorganize timer code into common path
feat(versal-net): introduce platform support
-rw-r--r-- | docs/plat/xilinx-versal_net.rst | 46 | ||||
-rw-r--r-- | plat/xilinx/common/timer/timers.c (renamed from plat/xilinx/versal/timers.c) | 10 | ||||
-rw-r--r-- | plat/xilinx/versal/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/xilinx/versal/platform.mk | 3 | ||||
-rw-r--r-- | plat/xilinx/versal_net/aarch64/plat_helpers.S | 73 | ||||
-rw-r--r-- | plat/xilinx/versal_net/include/platform_def.h | 122 | ||||
-rw-r--r-- | plat/xilinx/versal_net/include/util.h | 29 | ||||
-rw-r--r-- | plat/xilinx/versal_net/platform.mk | 28 | ||||
-rw-r--r-- | plat/xilinx/versal_net/tests_to_skip.txt | 63 | ||||
-rw-r--r-- | plat/xilinx/versal_net/versal_net_pwr_state.c | 59 | ||||
-rw-r--r-- | plat/xilinx/versal_net/versal_net_setup.c | 88 |
11 files changed, 516 insertions, 7 deletions
diff --git a/docs/plat/xilinx-versal_net.rst b/docs/plat/xilinx-versal_net.rst new file mode 100644 index 0000000..1886489 --- /dev/null +++ b/docs/plat/xilinx-versal_net.rst @@ -0,0 +1,46 @@ +.. + Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. ! + SPDX-License-Identifier: BSD-3-Clause ! + +Xilinx Versal NET +================= + +- The TF-A Tests on Xilinx Versal NET platform runs from DDR. +- Logs are available only on console and not saved in memory(No NVM support). +- Versal NET Platform uses TTC Timer + +Build Command +------------- +For individual tests/test suite: + +.. code-block:: shell + make CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net TESTS=<required tests> tftf +For Versal NET Specific tests (includes AMD-Xilinx Tests cases + Standard Test Suite) + +.. code-block:: shell + make CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net TESTS=versal tftf + +Execution on Target +------------------- + +- The TF-A Tests uses the memory location of U-boot. +- To package the tftf.elf in BOOT.BIN, the u-boot entry in bootgen.bif needs to be replaced with following + +.. code-block:: shell + the_ROM_image: + { + image { + { type=bootimage, file=project-spec/hw-description/system.pdi } + { type=bootloader, file=plm.elf } + { core=psm, file=psmfw.elf } + } + image { + id = 0x1c000000, name=apu_subsystem + { type=raw, load=0x00001000, file=system-default.dtb } + { core=a78-0, exception_level=el-3, trustzone, file=bl31.elf } + { core=a78-0, exception_level=el-1, file=tftf.elf } + } + } + +- The BOOT.BIN with TF-A Tests can now be used to run on the target. +- The TF-A Tests will be executed after TF-A and the tests report will be available on the console. diff --git a/plat/xilinx/versal/timers.c b/plat/xilinx/common/timer/timers.c index 5c1e8f5..a6e1afa 100644 --- a/plat/xilinx/versal/timers.c +++ b/plat/xilinx/common/timer/timers.c @@ -33,8 +33,6 @@ #define TTC_CLK_SEL_PS_REF BIT(0) #define TTC_CLK_SEL_RPU_REF BIT(4) -#define TIMER_IRQ U(69) - #define RET_SUCCESS U(0) /* @@ -136,12 +134,12 @@ static int handler_timer(void) return RET_SUCCESS; } -static const plat_timer_t versal_timers = { +static const plat_timer_t timers = { .program = program_timer, .cancel = cancel_timer, .handler = handler_timer, .timer_step_value = INTERVAL, - .timer_irq = TIMER_IRQ + .timer_irq = TTC_TIMER_IRQ }; int plat_initialise_timer_ops(const plat_timer_t **timer_ops) @@ -162,10 +160,10 @@ int plat_initialise_timer_ops(const plat_timer_t **timer_ops) */ timer_write_32(TTC_OFFSET_TMR_0 + TTC_CNT_CNTRL_OFFSET, 0x23); timer_write_32(TTC_OFFSET_TMR_0 + TTC_CLK_CNTRL_OFFSET, - CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN); + CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN); timer_write_32(TTC_OFFSET_TMR_0 + TTC_IER_OFFSET, 0x01); - *timer_ops = &versal_timers; + *timer_ops = &timers; return RET_SUCCESS; } diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h index dbc6845..925825c 100644 --- a/plat/xilinx/versal/include/platform_def.h +++ b/plat/xilinx/versal/include/platform_def.h @@ -115,4 +115,6 @@ /* LPD_SWDT_INT, AM011(v1.5), Chapter 50, Page 428 */ #define IRQ_TWDOG_INTID U(0x51) +#define TTC_TIMER_IRQ U(69) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk index 264ed3c..2161e89 100644 --- a/plat/xilinx/versal/platform.mk +++ b/plat/xilinx/versal/platform.mk @@ -4,6 +4,7 @@ # SPDX-License-Identifier: BSD-3-Clause # +XLNX_COMMON_PATH := plat/xilinx/common VERSAL_PATH := plat/xilinx/versal PLAT_INCLUDES := -I${VERSAL_PATH}/include/ @@ -18,7 +19,7 @@ PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \ ${VERSAL_PATH}/versal_setup.c \ ${VERSAL_PATH}/versal_pwr_state.c \ ${VERSAL_PATH}/aarch64/plat_helpers.S \ - ${VERSAL_PATH}/timers.c + ${XLNX_COMMON_PATH}/timer/timers.c PLAT_TESTS_SKIP_LIST := ${VERSAL_PATH}/tests_to_skip.txt diff --git a/plat/xilinx/versal_net/aarch64/plat_helpers.S b/plat/xilinx/versal_net/aarch64/plat_helpers.S new file mode 100644 index 0000000..77012ef --- /dev/null +++ b/plat/xilinx/versal_net/aarch64/plat_helpers.S @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <platform_def.h> + + .global platform_get_core_pos + .global plat_crash_console_init + .global plat_crash_console_flush + .global plat_crash_console_putc + +/*---------------------------------------------------------------------- + * unsigned int platform_get_core_pos(u_register_t mpid) + * + * Function to calculate the core position. + * + * clobbers: x0 - x3 + * --------------------------------------------------------------------- + */ +func platform_get_core_pos + /* x1 = core-id inside cluster */ + ubfx x1, x0, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS + /* x2 = cluster-id */ + ubfx x2, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS + + /* core-position = cluster-id * cores per cluster + core-id */ + mov x3, #PLATFORM_CORE_COUNT_PER_CLUSTER + madd x0, x2, x3, x1 + ret +endfunc platform_get_core_pos + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x4 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, CRASH_CONSOLE_BASE + mov_imm x1, PL011_UART_CLK_IN_HZ + mov_imm x2, PL011_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, CRASH_CONSOLE_BASE + b console_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------- + * int plat_crash_console_flush() + * Function to force a write of all buffered + * data that hasn't been output. + * Out : return -1 on error else return 0. + * Clobber list : r0 - r1 + * --------------------------------------------- + */ +func plat_crash_console_flush + mov_imm x1, CRASH_CONSOLE_BASE + b console_core_flush +endfunc plat_crash_console_flush diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h new file mode 100644 index 0000000..c357c96 --- /dev/null +++ b/plat/xilinx/versal_net/include/platform_def.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define TFTF_BASE U(0x8000000) + +#define CACHE_WRITEBACK_GRANULE U(0x40) + +#define PLATFORM_CLUSTER_COUNT U(4) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ + PLATFORM_CORE_COUNT_PER_CLUSTER) +#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \ + PLATFORM_CLUSTER_COUNT + 1) +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define PLAT_MAX_PWR_LEVEL MPIDR_AFFLVL2 +#define PLAT_MAX_PWR_STATES_PER_LVL U(2) + + +#define PLATFORM_STACK_SIZE U(0x440) +#define PCPU_DV_MEM_STACK_SIZE U(0x440) + + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define MAX_XLAT_TABLES U(8) +#define MAX_MMAP_REGIONS U(16) + +#define DRAM_BASE U(0x0) +#define DRAM_SIZE U(0x80000000) + +/* + * TFTF_NVM_OFFSET/SIZE correspond to the NVM partition in the partition + * table + */ +#define TFTF_NVM_SIZE U(0x600000) +#define TFTF_NVM_OFFSET U(0x20000000) + +/* Local state bit width for each level in the state-ID field of power state */ +#define PLAT_LOCAL_PSTATE_WIDTH U(4) + +/* GIC related addresses from datasheet */ +#define GICD_REG_BASE U(0xe2000000) +#define GICR_REG_BASE U(0xe2060000) + +/* GICv3 is used, dummy definition to resolve build failure */ +#define GICC_REG_BASE U(0xe2000000) + +/* + * Memory mapped devices that we must create MMU mappings for them + */ +#define GIC_BASE GICD_REG_BASE +#define GIC_SIZE U(0x01000000) + +#define TTC_BASE U(0xF1DC0000) +#define TTC_SIZE U(0x00010000) + +#define SYS_CNT_BASE1 TTC_BASE +#define SYS_CNT_SIZE TTC_SIZE + +#define LPD_IOU_SLCR U(0xF19A0000) +#define LPD_IOU_SLCR_SIZE U(0x00010000) + +/* ARM PL011 UART */ +#define PL011_UART0_BASE U(0xf1920000) +#define PL011_BAUDRATE U(115200) +#define PL011_UART_CLK_IN_HZ U(100000000) + +#define PLAT_ARM_UART_BASE PL011_UART0_BASE +#define PLAT_ARM_UART_SIZE U(0x1000) + +#define CRASH_CONSOLE_BASE PL011_UART0_BASE +#define CRASH_CONSOLE_SIZE PLAT_ARM_UART_SIZE + +/******************************************************************************* + * Non-Secure Software Generated Interrupts IDs + ******************************************************************************/ +#define IRQ_NS_SGI_0 0 +#define IRQ_NS_SGI_1 1 +#define IRQ_NS_SGI_2 2 +#define IRQ_NS_SGI_3 3 +#define IRQ_NS_SGI_4 4 +#define IRQ_NS_SGI_5 5 +#define IRQ_NS_SGI_6 6 +#define IRQ_NS_SGI_7 7 + +/* Per-CPU Hypervisor Timer Interrupt ID */ +#define IRQ_PCPU_HP_TIMER U(29) +/* Datasheet: TIME00 event*/ +#define IRQ_CNTPSIRQ1 U(29) + +/* Refer to AM011(v1.5), Chapter 50, Page 430 */ +#define PLAT_MAX_SPI_OFFSET_ID U(223) + +/* + * Times(in ms) used by test code for completion of different events. + */ +#define PLAT_SUSPEND_ENTRY_TIME U(15) +#define PLAT_SUSPEND_ENTRY_EXIT_TIME U(30) + +/* + * Dummy definitions that we need just to compile... + */ +#define ARM_SECURE_SERVICE_BUFFER_BASE U(0) +#define ARM_SECURE_SERVICE_BUFFER_SIZE U(100) + +/* LPD_SWDT_INT, AM011(v1.5), Chapter 50, Page 428 */ +#define IRQ_TWDOG_INTID U(0x51) + +#define TTC_TIMER_IRQ U(75) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/versal_net/include/util.h b/plat/xilinx/versal_net/include/util.h new file mode 100644 index 0000000..840c14f --- /dev/null +++ b/plat/xilinx/versal_net/include/util.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef UTIL_H +#define UTIL_H + +#include <platform_def.h> + +#define CPU_DEF(cluster, cpu) { cluster, cpu } + +#if (PLATFORM_CORE_COUNT_PER_CLUSTER == 1U) +#define CLUSTER_DEF(cluster) \ + CPU_DEF(cluster, 0) +#elif (PLATFORM_CORE_COUNT_PER_CLUSTER == 2U) +#define CLUSTER_DEF(cluster) \ + CPU_DEF(cluster, 0), \ + CPU_DEF(cluster, 1) +#elif (PLATFORM_CORE_COUNT_PER_CLUSTER == 4U) +#define CLUSTER_DEF(cluster) \ + CPU_DEF(cluster, 0), \ + CPU_DEF(cluster, 1), \ + CPU_DEF(cluster, 2), \ + CPU_DEF(cluster, 3) +#endif + +#endif /* UTIL_H */ diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk new file mode 100644 index 0000000..90d6d73 --- /dev/null +++ b/plat/xilinx/versal_net/platform.mk @@ -0,0 +1,28 @@ +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +XLNX_COMMON_PATH := plat/xilinx/common +VERSAL_NET_PATH := plat/xilinx/versal_net + +PLAT_INCLUDES := -I${VERSAL_NET_PATH}/include/ + +PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \ + drivers/arm/gic/gic_common.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + drivers/arm/pl011/${ARCH}/pl011_console.S \ + drivers/arm/timer/private_timer.c \ + drivers/console/console.c \ + ${VERSAL_NET_PATH}/versal_net_setup.c \ + ${VERSAL_NET_PATH}/versal_net_pwr_state.c \ + ${VERSAL_NET_PATH}/aarch64/plat_helpers.S \ + ${XLNX_COMMON_PATH}/timer/timers.c + +PLAT_TESTS_SKIP_LIST := ${VERSAL_NET_PATH}/tests_to_skip.txt + +ifeq ($(USE_NVM),1) +$(error "Versal NET port of TFTF doesn't currently support USE_NVM=1") +endif diff --git a/plat/xilinx/versal_net/tests_to_skip.txt b/plat/xilinx/versal_net/tests_to_skip.txt new file mode 100644 index 0000000..95f6c1e --- /dev/null +++ b/plat/xilinx/versal_net/tests_to_skip.txt @@ -0,0 +1,63 @@ +# +# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +# +################################################################################ +# Disable the listed tests for Versal NET Platform. +################################################################################ + +#TESTS: tftf-validation +Framework Validation/Events API +Framework Validation/NVM serialisation + +#TESTS: Timer framework Validation +Timer framework Validation + +#TESTS: Boot requirement tests +Boot requirement tests + +#TESTS: CPU Hotplug +CPU Hotplug/CPU hotplug +CPU Hotplug/CPU already on +CPU Hotplug/Context ID passing +CPU Hotplug/Invalid entry point + +#TESTS: PSCI System Suspend Validation +PSCI System Suspend Validation/System suspend with cores on +PSCI System Suspend Validation/Suspend system with cores in suspend + +#TESTS: CPU extensions +CPU extensions/PMUv3 SMC counter preservation + +#TESTS: Performance tests +Performance tests/Test cluster power up latency + +#TESTS: FF-A +FF-A Setup and Discovery/FF-A RXTX unmap SP rxtx buffer +FF-A Setup and Discovery/Test FFA_PARTITION_INFO_GET v1.0 +FF-A Memory Sharing/Lend memory, clear flag set +SIMD,SVE Registers context/Check that SIMD registers context is preserved +FF-A Interrupt +FF-A Notifications + +#TESTS: AMD-Xilinx tests +AMD-Xilinx tests + +#TESTS: psci +PSCI Affinity Info/Affinity info level0 powerdown +PSCI CPU Suspend/CPU suspend to powerdown at level 0 +PSCI CPU Suspend/CPU suspend to powerdown at level 1 +PSCI CPU Suspend/CPU suspend to powerdown at level 2 +PSCI CPU Suspend/CPU suspend to standby at level 0 +PSCI CPU Suspend/CPU suspend to standby at level 1 +PSCI CPU Suspend/CPU suspend to standby at level 2 +PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode +PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode +PSCI System Suspend Validation/System suspend multiple times +PSCI System Suspend Validation/system suspend from all cores +PSCI System Suspend Validation/Validate suspend to RAM functionality + +#TESTS: el3-power-state +EL3 power state parser validation diff --git a/plat/xilinx/versal_net/versal_net_pwr_state.c b/plat/xilinx/versal_net/versal_net_pwr_state.c new file mode 100644 index 0000000..a87331e --- /dev/null +++ b/plat/xilinx/versal_net/versal_net_pwr_state.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stddef.h> + +#include <arch.h> +#include <platform.h> +#include <psci.h> + +/* + * State IDs for local power states. + */ +#define VERSAL_NET_RETENTION_STATE_ID 1 /* Valid for only CPUs */ +#define VERSAL_NET_OFF_STATE_ID 0 /* Valid for CPUs and Clusters */ + +/* + * Suspend depth definitions for each power state + */ +typedef enum { + VERSAL_NET_RUN_DEPTH = 0, + VERSAL_NET_RETENTION_DEPTH, + VERSAL_NET_OFF_DEPTH, +} suspend_depth_t; + +/* The state property array with details of idle state possible for the core */ +static const plat_state_prop_t core_state_prop[] = { + {VERSAL_NET_RETENTION_DEPTH, VERSAL_NET_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY}, + {VERSAL_NET_OFF_DEPTH, VERSAL_NET_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +/* The state property array with details of idle state possible for the cluster */ +static const plat_state_prop_t cluster_state_prop[] = { + {VERSAL_NET_OFF_DEPTH, VERSAL_NET_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +/* The state property array with details of idle state possible for the system level */ +static const plat_state_prop_t system_state_prop[] = { + {VERSAL_NET_OFF_DEPTH, VERSAL_NET_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN}, + {0}, +}; + +const plat_state_prop_t *plat_get_state_prop(unsigned int level) +{ + switch (level) { + case MPIDR_AFFLVL0: + return core_state_prop; + case MPIDR_AFFLVL1: + return cluster_state_prop; + case MPIDR_AFFLVL2: + return system_state_prop; + default: + return NULL; + } +} diff --git a/plat/xilinx/versal_net/versal_net_setup.c b/plat/xilinx/versal_net/versal_net_setup.c new file mode 100644 index 0000000..40fe2c4 --- /dev/null +++ b/plat/xilinx/versal_net/versal_net_setup.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> + +#include <arch.h> +#include <drivers/arm/arm_gic.h> +#include <drivers/console.h> +#include <platform.h> +#include <tftf_lib.h> + +#include <platform_def.h> +#include <util.h> + +static const struct { + unsigned int cluster_id; + unsigned int cpu_id; +} versal_net_cores[PLATFORM_CORE_COUNT] = { + CLUSTER_DEF(0), + CLUSTER_DEF(1), + CLUSTER_DEF(2), + CLUSTER_DEF(3) +}; + + +static const mmap_region_t mmap[] = { + MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE, MT_MEMORY | MT_RW | MT_NS), + MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(CRASH_CONSOLE_BASE, CRASH_CONSOLE_SIZE, MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(TTC_BASE, TTC_SIZE, MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(LPD_IOU_SLCR, LPD_IOU_SLCR_SIZE, MT_DEVICE | MT_RW | MT_NS), + {0} +}; + +/* Power Domain Tree Descriptor array */ +const unsigned char versal_net_pwr_tree_desc[] = { + /* Number of root nodes */ + 1, + /* Number of clusters */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first cluster node */ + PLATFORM_CORE_COUNT_PER_CLUSTER, + PLATFORM_CORE_COUNT_PER_CLUSTER, + PLATFORM_CORE_COUNT_PER_CLUSTER, + PLATFORM_CORE_COUNT_PER_CLUSTER +}; + + +const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void) +{ + return versal_net_pwr_tree_desc; +} + +/* + * Generate the MPID from the core position. + */ +uint64_t tftf_plat_get_mpidr(unsigned int core_pos) +{ + assert(core_pos < PLATFORM_CORE_COUNT); + + return (uint64_t)make_mpid(versal_net_cores[core_pos].cluster_id, + versal_net_cores[core_pos].cpu_id); +} + +void tftf_plat_arch_setup(void) +{ + tftf_plat_configure_mmu(); +} + +void tftf_early_platform_setup(void) +{ + console_init(CRASH_CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); +} + +void tftf_platform_setup(void) +{ + arm_gic_init(GICC_REG_BASE, GICD_REG_BASE, GICR_REG_BASE); + arm_gic_setup_global(); + arm_gic_setup_local(); +} + +const mmap_region_t *tftf_platform_get_mmap(void) +{ + return mmap; +} |