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# Copyright (c) 2022, Arm Limited.
# SPDX-License-Identifier: MIT
%YAML 1.2
---
description: >-
Arm Architecture Envelope Model FVP configured with 8 CPUs across 2 clusters
(2x4) and 4GB DRAM. By default doesn't explicitly enable any architecture
features. Apply the architecture overlays at arch/v*.*.yaml to configure the
FVP for a sepcific architecture revision.
run:
name: FVP_Base_RevC-2xAEMvA
rtvars:
LOCAL_NET_PORT:
type: string
value: 8022
params:
# Basic dimensions for RAM and CPU.
-C bp.dram_size: 4
-C cluster0.NUM_CORES: 4
-C cluster1.NUM_CORES: 4
-C cluster0.PA_SIZE: 48
-C cluster1.PA_SIZE: 48
# Misc FVP controls.
--stat: null
-C bp.vis.disable_visualisation: 1
-C bp.refcounter.non_arch_start_at_default: 1 # Firmware is expected to enable the timer at boot time. However, turning this parameter on is a model-specific way of enabling the counter module out of reset.
-C bp.refcounter.use_real_time: 0 # Update the Generic Timer counter at a real-time base frequency instead of simulator time
-C bp.secure_memory: 1 # enable security checking by TZC-400
-C bp.ve_sysregs.exit_on_shutdown: 1 # SYS_CFG_SHUTDOWN exits simulation
-C pctl.startup: 0.0.0.0 # Comma-separated list of cores (wildcards allowed) to be powered up at startup or system reset
-C cluster0.clear_reg_top_eret: 2 # Behaviour of the upper 32-bits of the Xn registers when changing between AArch32 state and AArch64 state. 2: upper 32-bits set to 0 for a random selection of accessible registers.
-C cluster1.clear_reg_top_eret: 2
# Networking. By default use user-space networking, mapping port 22 in the
# FVP to a user-specified port on the host (see rtvar:LOCAL_NET_PORT). This
# enables ssh.
-C bp.smsc_91c111.enabled: 1
-C bp.hostbridge.userNetworking: 1
-C bp.hostbridge.userNetPorts: ${rtvar:LOCAL_NET_PORT}=22
# FVP Performance tweaks.
-C cache_state_modelled: 0 # Disable d-cache and i-cache state for all components
-C cluster0.stage12_tlb_size: 1024 # Increase TLB size from default of 128
-C cluster1.stage12_tlb_size: 1024
-C cluster0.check_memory_attributes: 0 # Disable checking that SW-set memory attributes conform to architecturally required constraints
-C cluster1.check_memory_attributes: 0
# GIC config options.
-C cluster0.gicv3.cpuintf-mmap-access-level: 2 # Allowed values are: 0-mmap access is supported for GICC,GICH,GICV registers. 1-mmap access is supported only for GICV registers. 2-mmap access is not supported.
-C cluster1.gicv3.cpuintf-mmap-access-level: 2
-C cluster0.gicv3.without-DS-support: 1 # GICv3 CPU interfaces do not support disabling security in the distributor
-C cluster1.gicv3.without-DS-support: 1
-C cluster0.gicv4.mask-virtual-interrupt: 1 # If true, virtual interrupts can be masked from being reported to virtual CPU interface by setting ICH_HCR_EL2.DVIM 1. No control otherwise.
-C cluster1.gicv4.mask-virtual-interrupt: 1
# These SMMU registers are configuring the arch model with a personality. Features to implement/expose.
# What is this personality?
-C pci.pci_smmuv3.mmu.SMMU_AIDR: 2
-C pci.pci_smmuv3.mmu.SMMU_IDR0: 0x0046123B
-C pci.pci_smmuv3.mmu.SMMU_IDR1: 0x00600002
-C pci.pci_smmuv3.mmu.SMMU_IDR3: 0x1714
-C pci.pci_smmuv3.mmu.SMMU_IDR5: 0xFFFF0475
-C pci.pci_smmuv3.mmu.SMMU_S_IDR1: 0xA0000002
-C pci.pci_smmuv3.mmu.SMMU_S_IDR2: 0
-C pci.pci_smmuv3.mmu.SMMU_S_IDR3: 0
# Enable virtio-rng. If Linux/DT is correctly configured, it can use this to
# speed up RNG init.
-C bp.virtio_rng.enabled: 1
terminals:
bp.terminal_0:
friendly: term0
port_regex: 'terminal_0: Listening for serial connection on port (\d+)'
type: stdout
bp.terminal_1:
friendly: term1
port_regex: 'terminal_1: Listening for serial connection on port (\d+)'
type: stdout
bp.terminal_2:
friendly: term2
port_regex: 'terminal_2: Listening for serial connection on port (\d+)'
type: stdout
bp.terminal_3:
friendly: term3
port_regex: 'terminal_3: Listening for serial connection on port (\d+)'
type: stdout
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