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authorNeil Armstrong <narmstrong@baylibre.com>2019-05-27 14:43:06 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2019-06-10 17:11:09 +0200
commitacdc8e71d9bb0bdef66b002f8baf8af3147df00c (patch)
tree7ffb96926677b90ee5fdfb93ae1084b61493507c /drivers/memstick
parent5a46b6fa0f33c2ca7a8432a0a48e1bf4a71fcc9f (diff)
mmc: meson-gx: add dram-access-quirk
On the Amlogic G12A SoC family, (only) the SDIO controller fails to access the data from DRAM, leading to a broken controller. But each MMC controller has 1,5KiB of SRAM after the registers, that can be used as bounce buffer to avoid direct DRAM access from the integrated DMAs (this SRAM may be used by the boot ROM when DRAM is not yet initialized). The quirk is to disable the chained descriptor for this controller, and use this SRAM memory zone as buffer for the bounce buffer fallback mode. The performance hit hasn't been evaluated, but the fix has been tested using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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