From 2035d77d790044f389a18c0e6baa05e86d4b32a0 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 29 Oct 2013 13:33:51 +0900 Subject: i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework This updates to new I2C framwwork on sh_i2c. And this also updates boards(kzm9g and ecovec) that using sh_i2c. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- README | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'README') diff --git a/README b/README index a70475fb05..9c6d058ef0 100644 --- a/README +++ b/README @@ -2040,6 +2040,24 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3 - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses + - drivers/i2c/sh_i2c.c: + - activate this driver with CONFIG_SYS_I2C_SH + - This driver adds from 2 to 5 i2c buses + + - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 + - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 + - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 + - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 + - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 + - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 + - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 + - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 + - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 + - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 + - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5 + - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 + - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses + additional defines: CONFIG_SYS_NUM_I2C_BUSES -- cgit v1.2.3 From 6789e84ecaa8f45d053084e08c381284a04abff7 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 22 Oct 2013 11:03:18 +0200 Subject: i2c, omap24xx: convert driver to new mutlibus/mutliadapter framework MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher Tested-by: Tom Rini Cc: Lars Poeschel Cc: Steve Sakoman Cc: Thomas Weber Cc: Tom Rix Cc: Grazvydas Ignotas Cc: Enric Balletbo i Serra Cc: Luca Ceresoli Cc: Igor Grinberg Cc: Ilya Yanok Cc: Stefano Babic Cc: Nishanth Menon Cc: Pali Rohár Cc: Peter Barada Cc: Nagendra T S Cc: Michael Jones Cc: Raphael Assenat Acked-by: Igor Grinberg Acked-by: Stefano Babic --- README | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'README') diff --git a/README b/README index 9c6d058ef0..53e56bb187 100644 --- a/README +++ b/README @@ -2058,6 +2058,19 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses + - drivers/i2c/omap24xx_i2c.c + - activate this driver with CONFIG_SYS_I2C_OMAP24XX + - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 + - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 + - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 + - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 + - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 + - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 + - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 + - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 + - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 + - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 + additional defines: CONFIG_SYS_NUM_I2C_BUSES -- cgit v1.2.3 From 0bdffe71fddeaa46768a39305797e4512dee0f15 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 8 Nov 2013 07:30:53 +0100 Subject: i2c, zynq: convert zynq i2c driver to new multibus/multiadapter framework - add zync i2c driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher Cc: Joe Hershberger Cc: Michal Simek --- README | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README') diff --git a/README b/README index 53e56bb187..c97ff0af0b 100644 --- a/README +++ b/README @@ -2071,6 +2071,11 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 + - drivers/i2c/zynq_i2c.c + - activate this driver with CONFIG_SYS_I2C_ZYNQ + - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting + - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr + additional defines: CONFIG_SYS_NUM_I2C_BUSES -- cgit v1.2.3 From 1df7bbba24b5f8f97331e30066358b7ab97ff1df Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Fri, 8 Nov 2013 01:03:50 +0200 Subject: README: document the CONFIG_GPIO_LED symbol The CONFIG_GPIO_LED symbol does not have any documentation in the README file. Document the CONFIG_GPIO_LED symbol. Signed-off-by: Igor Grinberg --- README | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'README') diff --git a/README b/README index c97ff0af0b..7b393b79b3 100644 --- a/README +++ b/README @@ -1963,6 +1963,14 @@ CBFS (Coreboot Filesystem) support kernel). Defining CONFIG_STATUS_LED enables this feature in U-Boot. + Additional options: + + CONFIG_GPIO_LED + The status LED can be connected to a GPIO pin. + In such cases, the gpio_led driver can be used as a + status LED backend implementation. Define CONFIG_GPIO_LED + to include the gpio_led driver in the U-Boot binary. + - CAN Support: CONFIG_CAN_DRIVER Defining CONFIG_CAN_DRIVER enables CAN driver support -- cgit v1.2.3 From 9dfdcdfed4726f94fc38d94f29f8214f38058576 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Fri, 8 Nov 2013 01:03:52 +0200 Subject: gpio_led: add support for inverted polarity Some GPIO connected LEDs have inverted polarity. Introduce new config option: CONFIG_GPIO_LED_INVERTED_TABLE for the specifying the inverted GPIO LEDs list and add support for this in the gpio_led driver. Signed-off-by: Igor Grinberg Tested-by: Ilya Ledvich --- README | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'README') diff --git a/README b/README index 7b393b79b3..5def773ff5 100644 --- a/README +++ b/README @@ -1971,6 +1971,13 @@ CBFS (Coreboot Filesystem) support status LED backend implementation. Define CONFIG_GPIO_LED to include the gpio_led driver in the U-Boot binary. + CONFIG_GPIO_LED_INVERTED_TABLE + Some GPIO connected LEDs may have inverted polarity in which + case the GPIO high value corresponds to LED off state and + GPIO low value corresponds to LED on state. + In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined + with a list of GPIO LEDs that have inverted polarity. + - CAN Support: CONFIG_CAN_DRIVER Defining CONFIG_CAN_DRIVER enables CAN driver support -- cgit v1.2.3 From 5614e71b4956c579cd4419b958b33fa6316eaa92 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 30 Sep 2013 09:22:09 -0700 Subject: Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun --- README | 41 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 5 deletions(-) (limited to 'README') diff --git a/README b/README index c97ff0af0b..49f4b3af2f 100644 --- a/README +++ b/README @@ -423,16 +423,47 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. - CONFIG_SYS_FSL_DDR_EMU - Specify emulator support for DDR. Some DDR features such as - deskew training are not available. - - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN Defines the endianess of the CPU. Implementation of those values is arch specific. + CONFIG_SYS_FSL_DDR + Freescale DDR driver in use. This type of DDR controller is + found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core + SoCs. + + CONFIG_SYS_FSL_DDR_ADDR + Freescale DDR memory-mapped register base. + + CONFIG_SYS_FSL_DDR_EMU + Specify emulator support for DDR. Some DDR features such as + deskew training are not available. + + CONFIG_SYS_FSL_DDRC_GEN1 + Freescale DDR1 controller. + + CONFIG_SYS_FSL_DDRC_GEN2 + Freescale DDR2 controller. + + CONFIG_SYS_FSL_DDRC_GEN3 + Freescale DDR3 controller. + + CONFIG_SYS_FSL_DDR1 + Board config to use DDR1. It can be enabled for SoCs with + Freescale DDR1 or DDR2 controllers, depending on the board + implemetation. + + CONFIG_SYS_FSL_DDR2 + Board config to use DDR2. It can be eanbeld for SoCs with + Freescale DDR2 or DDR3 controllers, depending on the board + implementation. + + CONFIG_SYS_FSL_DDR3 + Board config to use DDR3. It can be enabled for SoCs with + Freescale DDR3 controllers. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO @@ -3182,7 +3213,7 @@ FIT uImage format: CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT Set for the SPL on PPC mpc8xxx targets, support for - arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary. + drivers/ddr/fsl/libddr.o in SPL binary. CONFIG_SPL_COMMON_INIT_DDR Set for common ddr init with serial presence detect in -- cgit v1.2.3 From 9ac4ffbde1a5015c9929ee8578d3811b716e2fd3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 30 Sep 2013 14:20:51 -0700 Subject: Driver/DDR: Add Freescale DDR driver for ARM Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun --- README | 3 +++ 1 file changed, 3 insertions(+) (limited to 'README') diff --git a/README b/README index 49f4b3af2f..d6006f5018 100644 --- a/README +++ b/README @@ -450,6 +450,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DDRC_GEN3 Freescale DDR3 controller. + CONFIG_SYS_FSL_DDRC_ARM_GEN3 + Freescale DDR3 controller for ARM-based SoCs. + CONFIG_SYS_FSL_DDR1 Board config to use DDR1. It can be enabled for SoCs with Freescale DDR1 or DDR2 controllers, depending on the board -- cgit v1.2.3