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2013-06-26usb: musb: Use ARRAY_SIZE at appropriate placesAxel Lin
Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-06-26mtd: cfi_flash: Use ARRAY_SIZE at appropriate placesAxel Lin
Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-06-26hwmon: lm63: Use ARRAY_SIZE at appropriate placeAxel Lin
Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-06-26serial: Use ARRAY_SIZE instead of reinventing itAxel Lin
Signed-off-by: Axel Lin <axel.lin@ingics.com>
2013-06-26Fix block device accesses beyond 2TiBSascha Silbe
With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type, which is required to represent block numbers for storage devices that exceed 2TiB (the block size usually is 512B), e.g. recent hard drives. For some obscure reason, the current U-Boot code uses lbaint_t for the number of blocks to read (a rather optimistic estimation of how RAM sizes will evolve), but not for the starting address. Trying to access blocks beyond the 2TiB boundary will simply wrap around and read a block within the 0..2TiB range. We now use lbaint_t for block start addresses, too. This required changes to all block drivers as the signature of block_read(), block_write() and block_erase() in block_dev_desc_t changed. Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
2013-06-26cros: adds cros_ec keyboard driverHung-ying Tyan
This patch adds the driver for keyboard that's controlled by ChromeOS EC. Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: add LPC support for cros_ecHung-ying Tyan
This patch adds LPC support for carrying out the cros_ec protocol. Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: exynos: add SPI support for cros_ecHung-ying Tyan
This patch adds SPI support for carrying out the cros_ec protocol. Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: add I2C support for cros_ecHung-ying Tyan
This patch adds I2C support for carrying out the cros_ec protocol. Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2013-06-26cros: add cros_ec driverHung-ying Tyan
This patch adds the cros_ec driver that implements the protocol for communicating with Google's ChromeOS embedded controller. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
2013-06-24phylib: add atheros ar803x phyHeiko Schocher
add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
2013-06-24phylib: add natsemi dp83630 phyHeiko Schocher
add natsemi dp83630 phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
2013-06-24net: update FTGMAC100 for MMU/D-cache supportKuo-Jung Su
Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Tom Rini <trini@ti.com>
2013-06-24net: add Faraday FTMAC110 10/100Mbps ethernet supportKuo-Jung Su
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux. However it has a weird DMA alignment issue: (1) Tx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: O.K (2) Rx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: Invalid!!! Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
2013-06-24net: phy: supplement support for Micrel's KSZ9031SARTRE Leo
Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
2013-06-24net: macb: add support for gigabit MACBo Shen
Add gigabit MAC support in macb driver - using IP version to distinguish whether MAC is GMAC Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-06-24net: macb: using phylib to configure phy deviceBo Shen
using phylib to configure phy device in macb driver Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-06-24net: macb: using AT91FAMILY replace #ifdeferryBo Shen
Using CONFIG_AT91FAMILY replace #ifdeferry for atmel SoC Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-06-24net: ks8851_mll: add ethernet supportRoberto Cerati
The device interface is 16 bits wide. All the available packets are read from the incoming fifo. Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it> Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> [voice.shen@atmel.com: address comments from review results] [voice.shen@atmel.com: clean up for submit] Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
2013-06-24phylib: Add Atheros AR8035 GETH PHY supportXie Xiaobo
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2013-06-24add support for Xilinx 1000BASE-X phy (GTX)Charles Coldwell
commit 39695029bc15041c809df3db4ba19bd729c447fa Author: Charles Coldwell <coldwell@ll.mit.edu> Date: Tue Feb 19 08:27:33 2013 -0500 Changes to support the Xilinx 1000BASE-X phy (GTX/MGT) Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
2013-06-24PHY: micrel.c: add support for KSZ9031David Andrey
Add support for Micrel PHY KSZ9031 in phylib, including small rework for KSZ9021 to avoid code duplication Signed-off-by: David Andrey <david.andrey@netmodule.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Joe Herschberger <joe.hershberger@gmail.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
2013-06-24net: Fix build regression in macb.cJoe Hershberger
The added weak symbol must not be static. This was introduced in 416ce623fbad51af57660346ebb6f7befb88b3c9 Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2013-06-24net/macb: Add arch specific routine to get mdio controlShiraz Hashim
SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their respective phys. Currently there is a fixed configuration in which only a particular MAC can use the MDIO lines. Call an arch specific function to take control of specific mdio lines at runtime. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Acked-by: Stefan Roese <sr@denx.de>
2013-06-24net/designware: Do not select MIIPORT for RGMII interfaceVipin Kumar
Do not select MIIPORT for RGMII interface Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Acked-by: Stefan Roese <sr@denx.de>
2013-06-24NET: mvgbe: add support for DoveSebastian Hesselbarth
Marvell Dove also uses mvgbe as ethernet driver, therefore add support for Dove to reuse the current driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2013-06-24NET: mvgbe: add phylib supportSebastian Hesselbarth
This add phylib support to the Marvell GBE driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2013-06-24NET: phy: add 88E1310 PHY initializationSebastian Hesselbarth
This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2013-06-24net: add ICPlus PHY driverYegor Yefremov
The driver code was taken from Linux kernel source: drivers/net/phy/icplus.c Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2013-06-24phy: export genphy_parse_link()Yegor Yefremov
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2013-06-24net: Add sunxi (Allwinner) wemac driverHenrik Nordström
This patch adds support for the WEMAC, the ethernet controller included in the Allwinner A10 SoC. It will get used in the upcoming A10 board support. From: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
2013-06-24Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini
2013-06-23sf: Warn to use BAR for > 16MiB flashesJagannadha Sutradharudu Teki
Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: Add debug messages on spi_flash_read_commonJagannadha Sutradharudu Teki
- Added debug's on spi_flash_read_common() - Added space Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: Place the sf calls in proper orderJagannadha Sutradharudu Teki
Placed the sf calls in proper order - erase/write/read Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: Unify spi_flash write codeJagannadha Sutradharudu Teki
Move common flash write code into spi_flash_write_common(). Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Add flag status register polling supportJagannadha Sutradharudu Teki
Flag status register polling is required for micron 512Mb flash devices onwards, for performing erase/program operations. Like polling for WIP(Write-In-Progress) bit in read status register, spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control) bit in flag status register. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Remove spi_flash_cmd_poll_bit()Jagannadha Sutradharudu Teki
There is no other call other than spi_flash_cmd_wait_ready(), hence removed spi_flash_cmd_poll_bit and use the poll status code spi_flash_cmd_wait_ready() itself. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: spansion: Add support for S25FL512S_64KJagannadha Sutradharudu Teki
Add support for Spansion S25FL512S_64K SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: stmicro: Add support for N25Q1024AJagannadha Sutradharudu Teki
Add support for Numonyx N25Q1024A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: stmicro: Add support for N25Q1024Jagannadha Sutradharudu Teki
Add support for Numonyx N25Q1024 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: stmicro: Add support for N25Q512AJagannadha Sutradharudu Teki
Add support for Numonyx N25Q512A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: stmicro: Add support for N25Q512Jagannadha Sutradharudu Teki
Add support for Numonyx N25Q512 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23sf: Use spi_flash_addr() in write callJagannadha Sutradharudu Teki
Use the existing spi_flash_addr() for 3-byte addressing cmd filling in write call. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Add bank addr code in CONFIG_SPI_FLASH_BARJagannadha Sutradharudu Teki
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Update sf read to support all sizes of flashesJagannadha Sutradharudu Teki
This patch updated the spi_flash read func to support all sizes of flashes using bank reg addr facility. The same support has been added in below patch for erase/write spi_flash functions: "sf: Support all sizes of flashes using bank addr reg facility" (sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415) With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~460 bytes. sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Update sf to support all sizes of flashesJagannadha Sutradharudu Teki
Updated the spi_flash framework to handle all sizes of flashes using bank/extd addr reg facility The current implementation in spi_flash supports 3-byte address mode due to this up to 16Mbytes amount of flash is able to access for those flashes which has an actual size of > 16MB. As most of the flashes introduces a bank/extd address registers for accessing the flashes in 16Mbytes of banks if the flash size is > 16Mbytes, this new scheme will add the bank selection feature for performing write/erase operations on all flashes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Read flash bank addr register at probe timeJagannadha Sutradharudu Teki
Read the flash bank addr register to get the state of bank in a perticular flash. and also bank write happens only when there is a change in bank selection from user. bank read only valid for flashes which has > 16Mbytes those are opearted in 3-byte addr mode, each bank occupies 16Mytes. Suppose if the flash has 64Mbytes size consists of 4 banks like bank0, bank1, bank2 and bank3. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23sf: Discover the bank addr commandsJagannadha Sutradharudu Teki
Bank/Extended addr commands are specific to particular flash vendor so discover them based on the idocode0. Assign the discovered bank commands to spi_flash members so-that the bank read/write will use their specific operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 15:10:03 +0000