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AgeCommit message (Expand)Author
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni
2024-01-09aarch64: Regenerate aarch64-*-2.c filesVictor Do Nascimento
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento
2024-01-09aarch64: Add xs variants of tlbip operandsVictor Do Nascimento
2024-01-09aarch64: Implement TLBIP 128-bit instructionVictor Do Nascimento
2024-01-09aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macrosVictor Do Nascimento
2024-01-09aarch64: Apply narrowing of allowed immediate values for SYSPVictor Do Nascimento
2024-01-09aarch64: Add support for the SYSP 128-bit system instructionVictor Do Nascimento
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento
2024-01-09aarch64: Expand maximum number of operands from 5 to 6Victor Do Nascimento
2024-01-09aarch64: Add +d128 architectural feature supportVictor Do Nascimento
2024-01-08aarch64: Add ite feature system registers.srinath
2024-01-07i386: Correct adcx suffix in disassemblerH.J. Lu
2024-01-05Add AMD znver5 processor supportTejas Joshi
2024-01-05x86: corrections to CPU attribute/flags splittingJan Beulich
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma
2024-01-04Update year range in copyright notice of binutils filesAlan Modra
2024-01-04LoongArch: Fix some macro that cannot be expanded properlyLulu Cai
2023-12-30LoongArch: Commas inside double quotesAlan Modra
2023-12-29LoongArch: opcodes: Add support for tls le relax.changjiachen
2023-12-29RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma
2023-12-28Support APX JMPABS for disassemblerHu, Lin1
2023-12-28Support APX pushp/poppCui, Lili
2023-12-28Support APX Push2/Pop2Mo, Zewei
2023-12-28Support APX NDDkonglin1
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai
2023-12-25Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">Alan Modra
2023-12-20s390: Add suffix to conditional branch instruction descriptionsJens Remus
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus
2023-12-20s390: Use safe string functions and length macros in s390-mkopcJens Remus
2023-12-20s390: Enhance error handling in s390-mkopcJens Remus
2023-12-20s390: Provide IBM z16 (arch14) instruction descriptionsJens Remus
2023-12-20s390: Align letter case of instruction descriptionsJens Remus
2023-12-20s390: Fix build when using EXEEXT_FOR_BUILDJens Remus
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo
2023-12-19aarch64: Add FEAT_ECBHB supportAndrea Corallo
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang
2023-12-18LoongArch: Add call36 and tail36 pseudo instructions for medium code modelmengqinggang
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich
2023-12-15x86: fold assembly dialect attributesJan Beulich
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma
2023-12-14Remove redundant Byte, Word, Dword and Qword from insn templates.Cui, Lili
2023-12-13Make const_1_mode print $1 in AT&T syntaxCui, Lili