thiago.bauermann/binutils-gdb.git

Age	Commit message (Expand)	Author
2024-01-05	RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli	Jin Ma
2024-01-04	Update year range in copyright notice of binutils files	Alan Modra
2023-12-29	RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension	Jin Ma
2023-12-14	RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.	Jin Ma
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu
2023-12-01	RISC-V: Zv*: Add support for Zvkb ISA extension	Christoph Müllner
2023-11-24	RISC-V: drop leftover match_never() references	Jan Beulich
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich
2023-11-24	RISC-V: disallow x0 with certain macro-insns	Jan Beulich
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add reductions instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...	Jin Ma
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett
2023-11-03	RISC-V: reduce redundancy in load/store macro insn handling	Jan Beulich
2023-09-07	RISC-V: Clarify the naming rules of vendor operands.	Nelson Chu
2023-09-05	RISC-V: fold duplicate code in vector_macro()	Jan Beulich
2023-09-01	RISC-V: move various alias entries	Jan Beulich
2023-08-30	RISC-V: Make XVentanaCondOps RV64 only	Tsukasa OI
2023-08-15	RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'	Tsukasa OI
2023-08-15	RISC-V: Add support for the 'Zihintntl' extension	Tsukasa OI
2023-08-15	RISC-V: remove indirection from register tables	Jan Beulich
2023-08-11	RISC-V: Fix opcode entries of "vmsge{,u}.vx"	Tsukasa OI
2023-08-07	RISC-V: move comment describing rules for riscv_opcodes[]	Jan Beulich
2023-08-02	Revert "2.41 Release sources"	Sam James
2023-08-02	2.41 Release sources	Nick Clifton
2023-07-18	RISC-V: Supports Zcb extension.	Jiawei
2023-07-01	RISC-V: Add support for the Zvksh ISA extension	Christoph Müllner
2023-07-01	RISC-V: Add support for the Zvksed ISA extension	Christoph Müllner
2023-07-01	RISC-V: Add support for the Zvknh[a,b] ISA extensions	Christoph Müllner
2023-07-01	RISC-V: Add support for the Zvkned ISA extension	Christoph Müllner
2023-07-01	RISC-V: Add support for the Zvkg ISA extension	Christoph Müllner
2023-07-01	RISC-V: Add support for the Zvbc extension	Nathan Huckleberry
2023-07-01	RISC-V: Add support for the Zvbb ISA extension	Christoph Müllner
2023-06-30	RISC-V: Add support for the Zfa extension	Christoph Müllner
2023-06-27	RISC-V: Support Zicond extension	Philipp Tomsich
2023-06-01	RISC-V: PR30449, Add lga assembler macro support.	Jim Wilson
2023-04-26	RISC-V: Support XVentanaCondOps extension	Philipp Tomsich
2023-03-31	RISC-V: Allocate "various" operand type	Tsukasa OI
2023-01-31	RISC-V: make C-extension JAL available again for (32-bit) assembly	Jan Beulich
2023-01-01	Update year range in copyright notice of binutils files	Alan Modra
2022-11-17	RISC-V: Add T-Head Int vendor extension	Christoph Müllner
2022-11-17	RISC-V: Add T-Head Fmv vendor extension	Christoph Müllner