thiago.bauermann/binutils-gdb.git

Age	Commit message (Expand)	Author
2024-01-05	RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli	Jin Ma
2024-01-04	Update year range in copyright notice of binutils files	Alan Modra
2023-12-01	RISC-V: Make riscv_is_mapping_symbol stricter	Patrick O'Neill
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu
2023-11-30	RISC-V: Avoid updating state until symbol is found	Patrick O'Neill
2023-11-24	RISC-V: disallow x0 with certain macro-insns	Jan Beulich
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett
2023-10-13	RISC-V: Add support for numbered ISA mapping strings	Joseph Faulls
2023-09-07	RISC-V: Clarify the naming rules of vendor operands.	Nelson Chu
2023-08-15	RISC-V: remove indirection from register tables	Jan Beulich
2023-08-02	Revert "2.41 Release sources"	Sam James
2023-08-02	2.41 Release sources	Nick Clifton
2023-07-28	Fix typo in riscv-dis.c comment	Tsukasa OI
2023-07-18	RISC-V: Supports Zcb extension.	Jiawei
2023-07-01	RISC-V: Add support for the Zvbb ISA extension	Christoph Müllner
2023-06-30	RISC-V: Add support for the Zfa extension	Christoph Müllner
2023-05-19	RISC-V: Minor improvements for dis-assembler.	Nelson Chu
2023-04-18	RISC-V: Cache the latest mapping symbol and its boundary.	Kito Cheng
2023-03-31	RISC-V: Allocate "various" operand type	Tsukasa OI
2023-03-21	RISC-V: Fix disassemble fetch fail return value.	Jiawei
2023-02-03	RISC-V: don't disassemble unrecognized insns as .byte	Jan Beulich
2023-01-01	Update year range in copyright notice of binutils files	Alan Modra
2022-11-28	RISC-V: Better support for long instructions (disassembler)	Tsukasa OI
2022-10-28	RISC-V: Output mapping symbols with ISA string.	Nelson Chu
2022-10-14	opcodes/riscv-dis.c: Remove last_map_state	Tsukasa OI
2022-10-14	opcodes/riscv-dis.c: Make XLEN variable static	Tsukasa OI
2022-10-14	opcodes/riscv-dis.c: Use bool type whenever possible	Tsukasa OI
2022-10-14	opcodes/riscv-dis.c: Tidying with spacing	Tsukasa OI
2022-10-14	opcodes/riscv-dis.c: Tidying with comments/clarity	Tsukasa OI
2022-10-06	RISC-V: Print XTheadMemPair literal as "immediate"	Tsukasa OI
2022-10-06	RISC-V: Fix T-Head immediate types on printing	Tsukasa OI
2022-10-06	RISC-V: Print comma and tabs as the "text" style	Tsukasa OI
2022-10-06	RISC-V: Optimize riscv_disassemble_data printf	Tsukasa OI
2022-10-06	RISC-V: Fix printf argument types corresponding %x	Tsukasa OI
2022-10-06	RISC-V: Fix immediates to have "immediate" style	Tsukasa OI
2022-10-04	RISC-V: Fix buffer overflow on print_insn_riscv	Tsukasa OI
2022-10-04	opcodes/riscv: style csr names as registers	Andrew Burgess
2022-09-30	RISC-V: fix build after "Add support for arbitrary immediate encoding formats"	Jan Beulich
2022-09-22	RISC-V: Add support for literal instruction arguments	Christoph Müllner
2022-09-22	RISC-V: Add support for arbitrary immediate encoding formats	Christoph Müllner
2022-09-22	RISC-V: Remove "b" operand type from disassembler	Tsukasa OI
2022-09-06	opcodes: Add non-enum disassembler options	Tsukasa OI
2022-09-02	RISC-V: Print highest address (-1) on the disassembler	Tsukasa OI
2022-09-02	RISC-V: PR29342, Fix RV32 disassembler address computation	Tsukasa OI
2022-07-07	RISC-V: Fix disassembling Zfinx with -M numeric	Tsukasa OI
2022-04-30	opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblers	Thomas Hebb
2022-04-04	opcodes/riscv: implement style support in the disassembler	Andrew Burgess
2022-03-18	RISC-V: Prefetch hint instructions and operand set	Tsukasa OI