| Age | Commit message (Expand) | Author |
|---|
| 2024-01-04 | Update year range in copyright notice of binutils files | Alan Modra |
| 2023-12-28 | Support APX pushp/popp | Cui, Lili |
| 2023-12-28 | Support APX NDD | konglin1 |
| 2023-12-28 | Support APX GPR32 with extend evex prefix | Cui, Lili |
| 2023-12-28 | Support APX GPR32 with rex2 prefix | Cui, Lili |
| 2023-12-19 | x86: Remove the restriction for size of the mask register in AVX10 | Haochen Jiang |
| 2023-12-15 | x86: fold assembly dialect attributes | Jan Beulich |
| 2023-11-09 | x86: split insn templates' CPU field | Jan Beulich |
| 2023-10-31 | Support Intel USER_MSR | Hu, Lin1 |
| 2023-09-15 | x86: fold CpuLM and Cpu64 | Jan Beulich |
| 2023-09-14 | x86: support AVX10.1 vector size restrictions | Jan Beulich |
| 2023-09-01 | x86: rename CpuPCLMUL | Jan Beulich |
| 2023-08-11 | x86: pack CPU flags in opcode table | Jan Beulich |
| 2023-08-02 | Revert "2.41 Release sources" | Sam James |
| 2023-08-02 | 2.41 Release sources | Nick Clifton |
| 2023-07-27 | Support Intel PBNDKB | Hu, Lin1 |
| 2023-07-27 | Support Intel SM4 | Haochen Jiang |
| 2023-07-27 | Support Intel SM3 | Haochen Jiang |
| 2023-07-27 | Support Intel SHA512 | Haochen Jiang |
| 2023-07-27 | Support Intel AVX-VNNI-INT16 | konglin1 |
| 2023-06-16 | x86: shrink Masking insn attribute to a single bit (boolean) | Jan Beulich |
| 2023-05-23 | Support Intel FRED LKGS | Zhang, Jun |
| 2023-05-23 | Revert "Support Intel FRED LKGS" | liuhongt |
| 2023-05-23 | Support Intel FRED LKGS | Zhang, Jun |
| 2023-04-07 | Support Intel AMX-COMPLEX | Haochen Jiang |
| 2023-03-31 | x86: parse VEX and alike specifiers for .insn | Jan Beulich |
| 2023-03-20 | x86: VexVVVV is now merely a boolean | Jan Beulich |
| 2023-02-24 | x86: MONITOR/MWAIT are not SSE3 insns | Jan Beulich |
| 2023-02-24 | x86-64: don't permit LAHF/SAHF with "generic64" | Jan Beulich |
| 2023-02-10 | x86: drop use of VEX3SOURCES | Jan Beulich |
| 2023-02-10 | x86: drop use of XOP2SOURCES | Jan Beulich |
| 2023-02-10 | x86: move (and rename) opcodespace attribute | Jan Beulich |
| 2023-01-27 | x86: use ModR/M for FPU insns with operands | Jan Beulich |
| 2023-01-20 | x86: embed register names in reg_entry | Jan Beulich |
| 2023-01-20 | x86: move insn mnemonics to a separate table | Jan Beulich |
| 2023-01-01 | Update year range in copyright notice of binutils files | Alan Modra |
| 2022-12-21 | x86: rename CheckRegSize to CheckOperandSize | Jan Beulich |
| 2022-12-12 | x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodes | Jan Beulich |
| 2022-12-01 | x86: drop No_ldSuf | Jan Beulich |
| 2022-11-30 | x86: drop FloatR | Jan Beulich |
| 2022-11-17 | i386: Move i386_seg_prefixes to gas | H.J. Lu |
| 2022-11-15 | Add AMD znver4 processor support | Tejas Joshi |
| 2022-11-14 | x86: fold special-operand insn attributes into a single enum | Jan Beulich |
| 2022-11-08 | Support Intel RAO-INT | Kong Lingling |
| 2022-11-04 | Support Intel AVX-NE-CONVERT | konglin1 |
| 2022-11-02 | Support Intel MSRLIST | Hu, Lin1 |
| 2022-11-02 | Support Intel WRMSRNS | Hu, Lin1 |
| 2022-11-02 | Support Intel CMPccXADD | Haochen Jiang |
| 2022-11-02 | Support Intel AVX-VNNI-INT8 | Cui,Lili |
| 2022-11-02 | Support Intel AVX-IFMA | Hongyu Wang |
