thiago.bauermann/binutils-gdb.git

Age	Commit message (Expand)	Author
2024-01-15	aarch64: Add support for FEAT_SME2p1 instructions.	Srinath Parvathaneni
2024-01-15	aarch64: Add support for FEAT_B16B16 instructions.	Srinath Parvathaneni
2024-01-12	aarch64: Add +xs flag for existing instructions	Andrew Carlotti
2024-01-12	aarch64: Add +wfxt flag for existing instructions	Andrew Carlotti
2024-01-12	aarch64: Add +rcpc2 flag for existing instructions	Andrew Carlotti
2024-01-12	aarch64: Add +jscvt flag for existing fjcvtzs instruction	Andrew Carlotti
2024-01-10	gas: aarch64: Add system registers for Debug and PMU extensions	Saurabh Jha
2024-01-09	Synchronize sourceware version of the libiberty sources with the master gcc v...	Nick Clifton
2024-01-09	aarch64: ADD FEAT_THE RCWCAS instructions.	Srinath Parvathaneni
2024-01-09	aarch64: Add support for 128-bit system register mrrs and msrr insns	Victor Do Nascimento
2024-01-09	aarch64: Implement TLBIP 128-bit instruction	Victor Do Nascimento
2024-01-09	aarch64: Apply narrowing of allowed immediate values for SYSP	Victor Do Nascimento
2024-01-09	aarch64: Add support for optional operand pairs	Victor Do Nascimento
2024-01-09	aarch64: Add support for xzr register in register pair operands	Victor Do Nascimento
2024-01-09	aarch64: Expand maximum number of operands from 5 to 6	Victor Do Nascimento
2024-01-09	aarch64: Add +d128 architectural feature support	Victor Do Nascimento
2024-01-08	arm: Add support for Armv8.9-A and Armv9.4-A	srinath
2024-01-05	RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli	Jin Ma
2024-01-04	Update year range in copyright notice of binutils files	Alan Modra
2023-12-29	LoongArch: include: Add support for tls le relax.	changjiachen
2023-12-28	x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESC	H.J. Lu
2023-12-28	x86-64: Add R_X86_64_CODE_4_GOTPCRELX	H.J. Lu
2023-12-28	x86: Add NT_X86_SHSTK note	Schimpe, Christina
2023-12-28	Support APX GPR32 with rex2 prefix	Cui, Lili
2023-12-25	LoongArch: Add support for TLS LD/GD/DESC relaxation	mengqinggang
2023-12-25	LoongArch: Add tls transition support.	Lulu Cai
2023-12-25	LoongArch: Add new relocs and macro for TLSDESC.	Lulu Cai
2023-12-20	s390: Optionally print instruction description in disassembly	Jens Remus
2023-12-19	aarch64: Add FEAT_ITE support	Andrea Corallo
2023-12-19	aarch64: Add FEAT_SPECRES2 support	Andrea Corallo
2023-12-18	LoongArch: Add new relocation R_LARCH_CALL36	mengqinggang
2023-12-14	RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.	Jin Ma
2023-12-10	Add some new DW_IDX_* constants	Tom Tromey
2023-12-05	Add basic support for RISC-V 64-bit EFI objects	Andreas Schwab
2023-12-04	s390: Support for jump visualization in disassembly	Jens Remus
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu
2023-12-01	RISC-V: Zv*: Add support for Zvkb ISA extension	Christoph Müllner
2023-11-28	libiberty, ld: Use x86 HW optimized sha1	Jakub Jelinek
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma
2023-11-23	RISC-V: Add T-Head VECTOR vendor extension.	Jin Ma
2023-11-16	aarch64: Add support for VMSA feature enhancements.	Srinath Parvathaneni